gaurav_brcm

Members
  • Content count

    17
  • Joined

  • Last visited

About gaurav_brcm

  • Rank
    Member

Profile Information

  • Gender
    Not Telling
  1. Hi All, I wanted to know the usage of get_hdl_path() and get_full_hdl_path(). Any example would be helpful. I have added set_hdl_path_root for register block on top level and added add_hdl_path for different registers such as : add_hdl_path ('{ '{"RegA", -1 , -1} }); for RegA add_hdl_path ('{ '{"RegB", -1 , -1} }); for RegB And this line in register block : this.set_hdl_path_root("top.dut", "RTL"); Now I want to know what HDL path is getting used while doing peek method ? Thanks, Gaurav
  2. Hi Roman, Is there any documents for this ? I also want to know and use UVM memory manager, but can hardly find any examples and documentation. Thanks, Gaurav
  3. Hi agnesmary, I also had this problem, finally I got reference from Verification Academy forum. Basically after including and setting coverage, you will have to call sample_values from your testbench. Then it will work.
  4. Hi, I am facing the same problem. Should set_coverage be called only after build_phase ? Thanks.
  5. Thanks Uwe, As you pointed out I am seeing empty coverage. In my case, RAL model generator creates protected virtual function of sample. Probably I will need to override or trigger that for correct sampling.
  6. Hi, I want to use in-built UVM RAL cover groups. I tried following steps but did not help : 1) Enable coverage building: Before building register model, I use following : uvm_reg::include_coverage("*",UVM_CVR_ALL); 2) To enable sampling : <_regmodel>.set_coverage(UVM_CVR_ALL); In my regmodel there are two types of cover groups: UVM_CVR_ADDR_MAP in top level register model and UVM_CVR_REG_BITS in individual registers. I was hoping that UVM_CVR_ALL would enable sampling of all. I could see cover groups getting built but are not sampled. Am I missing something ? Please let me know. Thanks.
  7. Hi, I have following scenario : 1) There are backdoor writes without using RAL to some registers. 2) I want to run reset sequence. Now for this first I want to update mirrored values of registers with backdoor values. Then check those values. What is the method for this ? What is correct way for testing in this scenario ? Thanks.
  8. Hi Uwes, Thanks for your reply. Yes it is just printing problem. - Gaurav
  9. No I have fields defined between 28 to 31 and thats what amazes me. These are defined as : field_b.configure(this, 1, 31, "RW", 0, 1'h1, 1, 1, 1) field_c.configure(this, 2, 29, "RW", 0, 2'h0, 1, 1, 1) So X should not in bit 29 , 30 , 31.
  10. Actually there is one problem here : Though only [28:17] are set for UVM_NO_CHECK, mirrored value extends it till 31 , which is wrong. Thanks, Gaurav
  11. Thanks a lot for your reply Tudor. Helps a lot.
  12. Hi All, I am facing an issue: One of the register field is configured as : field_a.configure(this, 12, 17, "RO", 0, 12'h0, 1, 0, 1); field_a.set_compare(UVM_NO_CHECK); While doing a reset test, first I reset model then start test. But test fails with : UVM_ERROR -- value read from DUT (0x0000000080001e00) does not match mirrored value (0x00000000XxxXfe00) Basically the fields declared as RO and UVM_NO_CHECK goes X ? Any idea what I am missing or doing wrong ? Thanks.
  13. Thanks for pointing the link . Helps a lot. Regards, GG
  14. Hi All, This may seem to be a basic question. But I need to know methodology and correct way of doing it. If I have to wait for some clocks in sequence , how do we achieve it ? 1) In driver , we have interface handle so there we can wait and use uvm_event ?? 2) Use #delays in sequence . Please let me know the correct method. Thanks, GG
  15. Hi uwes, Thanks for reply. The posted code is just for description. The tool reports the contradiction error by showing the value of variable in child sequence and the value in the top sequence . So what is the UVM way of changing the value in child sequences from virtual sequences ? Regards, GG