During the compilation process, my code met two make erros: make: *** No rule to make target `/proj/verif_release_ro/ovmkit_o2.1.2_u1.1b/14/uvm/src/dpi/uvm_dpi.c', needed by `uvm_dpi.o'. Stop. make: Leaving directory `.../src/verif/interface/master/examples/master_b2b_test/csrc' Could anybody tell me what this problem is? Thank you very much in advance!
liya posted a topic in UVM SystemVerilog Discussionshi, all, I'm a newer in learning UVM. With the support of many UVM experts, we can find many examples for learnning UVM. However, when I tried to have a taste on some examples using VCS to compile them, the Makefile is a headache for me. Could you please let me know how to write a good Makefile for compilation and running simulation in VCS? Thank you in advance! Liya