Dear all,
up to my knowledge, there are two main verification environments/libraries/methodologies for SystemC (and SystemC TLM). That is SystemC Verification Environment (SCV) and SystemC UVM from Cadence.
SCV development stopped in 2006. Do you know what is the current status of the Verification Group? Is there any plan of further improvements?
UVM, w.r.t. SCV, is a more robust methodology but still SystemC UVM provided by Cadence is a "Prodigal Son" if compared with the SystemVerilog support of UVM.
Are you aware of any other solution for verification of SystemC designs? SCV and SystemC UVM are simulation based approaches? Do you know any available formal-technique-based verification tool for SystemC (e.g., a model checker)?
Thanks!