GiuseppeDiGuglielmo

Hello Alan, I am not able to join the group. The authentication form does not let me in. The group page says: Join this Working Group If you are an employee of a member company and would like to join this working group,click here (requires login) and click Join Group. WG participation requires right of entry by the group chair. I am a researcher at Columbia University, not a employee of a member company. Can I join the group too?

Hi Hans, I am aware of that. This is an image that I use in my presentations: Yes. SCV is definitely complex for people who are used to Verilog or VHDL but not C++. The introspection/extension stuff could be "cumbersome" sometimes. I am using Cadence NCsim. I will check if any difference exist between SCV 2006 (Accellera) and the Cadence SCV. Most likely Cadence guys are just supporting the latest GNU g++ compiler, as I did (some patches and still a lot of warnings in compilation). Yes indeed. I consider SCV just a library (let's call it a toolbox) and UVM a methodology. But I am not sure if in UVM I can use SCV or if SCV is deprecated and I have to use e language. What do you think?

Hi, do you have any link?

Dear all, up to my knowledge, there are two main verification environments/libraries/methodologies for SystemC (and SystemC TLM). That is SystemC Verification Environment (SCV) and SystemC UVM from Cadence. SCV development stopped in 2006. Do you know what is the current status of the Verification Group? Is there any plan of further improvements? UVM, w.r.t. SCV, is a more robust methodology but still SystemC UVM provided by Cadence is a "Prodigal Son" if compared with the SystemVerilog support of UVM. Are you aware of any other solution for verification of SystemC designs? SCV and SystemC UVM are simulation based approaches? Do you know any available formal-technique-based verification tool for SystemC (e.g., a model checker)? Thanks!