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manikanta.mashetti

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About manikanta.mashetti

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  • Birthday 06/07/1991

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  1. manikanta.mashetti

    Can we write RTL(Register Transfer Level) using SystemC?

    Thank You.. David Black and Dakupoto
  2. manikanta.mashetti

    Can we write RTL(Register Transfer Level) using SystemC?

    Thank You Fitch, From that thread, I got many things. But few more is 1. SystemC is mainly used by the system Architects. We also have a tools for RTL modeling (Forte Design Systems Cynthesizer, or Xilinx Vivado HLS) then why the designs are not implemented using SystemC? 2. Once the design is also implemented by using SystemC, then it will be very useful to the company with respect to time, money, human forces. But why only people using this language at system level.? Is there any problems with systemC to describe the language at RTL level. 3. If we implement the IP in any language, it will be reused in another project(If that same IP comes in to that project also). This is true in any IP. But why Systemc people specially press this point as one of the advantage of Systemc? Can you please clarify this .... Thanks & regards Mani
  3. Hi , Recently I have studied that SystemC can be used To model High level functional models to detailed clock cycle accurate RTL models. If any company done like this then the they can save the time and energy too. Because at different levels we are using the same language. But as of my knowledge many companies uses SystemC at system Modeling only. Why they are not using the same language at RTL instead it has many advantages. ? Please clear this doubt Thanks, Mani
  4. manikanta.mashetti

    What is Validation in systemC?

    I studied that, SystemC is useful to know the problems early in the design cycles, like verification, validation, and software development. But how SystemC is useful in the case of validation and software development, please explain ?
  5. manikanta.mashetti

    Schematic Tracer

    Can we see the schematic view of the designs in Cadence Simvision? Language used for design is SystemC.
  6. manikanta.mashetti

    Tracing internal signals declared in sc_module using sc_trace

    hi In the sc_main(), you have to instantiate DUT module with some instance name use that instance name to trace the signal, like in your example only clk_dut mod1("DUT"); ... ... sc_trace(fp,mod1.temp,"TEMP");
  7. manikanta.mashetti

    Method Process

    Thanks for reply, Actually I am modelling a processor using system C, In this in the ALU (execute stage), one method is there in that depending on the signals coming from the decode stage it triggers, in this case I should signals in the sensitivity list(other than clock), so here only I am getting the problem. It triggers more no of times at a same simulation time. And I checked with sc_delta_count(), at same simulation time it is giving two count values. How will I resolve this.
  8. manikanta.mashetti

    Method Process

    thank you for your reply, I am the beginner to system C, what is delta ? can you give me the hint how to rewrite the code, so that the signals that are sensitive to change on the same delta ?
  9. manikanta.mashetti

    Method Process

    Hello, In system C, A method is called when ever the event in the sensitivity list changes. Like always block in Verilog. Triggering event in sensitive list can be either edge sensitive or level sensitive. But at the same simulation time, more than one signal in the sensitivity list changes then that method will be triggered more than once, so at the same simulation time the method is executed more no of times, where as in verilog always block after all signals finalized it enters in to the block, how will I overcome this problem in systemC. Eg: SC_METHOD(writing_to_memory); sensitive<<data<<address<<rst; void writing_to_memory() { ----- ----- } In the above example at the simulation time of 100ns, data is changed, and address also changed so the method will be called twice and executed twice..But I don't want this type of bahaviour how will implement.. please help me... thank you..
  10. manikanta.mashetti

    Why systemC?

    Hi, I have some doubts regarding systemC, please help me What are the main advantages of systemC compare to the other modelling languages? why architects choose this language ? In the Behavioural Modelling how ever we are implementing the functionality using systemC, with this model we can move from netlist to GDSII, but this model is not used for synthesis, and we are again writing the RTL coding and move to the futher steps, why? Why many companies are not using SystemC?
  11. Hi, I would like to know what all these terms, what is the difference between each one.
  12. manikanta.mashetti

    not gate with sc_logic

    Use internal variable of type logic in the proc copy the input value in to this variable then invert variable and assign to the output port.
  13. manikanta.mashetti

    Type casting && Floating point nos.

    Hie Philipp, I got a clear Idea now ..and I got a solution for my problem....but If I use this nonstandard classes ,Is my code is synthesisable.? what is exactly nonstandard classes... Thank You...
  14. manikanta.mashetti

    Type casting && Floating point nos.

    hello, If I do like that ,bit vector to integer conversion is fine,but integer to float it doesn't work correctly.. Eg: If I want to store 125.2345...If i do conversion from (float -> bitvector -> integer -> float) ,float stores only 125.0 but I want to retrieve back same data(125.2345).
  15. manikanta.mashetti

    Type casting && Floating point nos.

    This I got it sir,suppose if I want to do the reverse conversion (bitvector to float). how should I proceed...Is there any non standard classes like above... or give me some hint I will try to solve.. thank you.
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