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Hany Salah

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  1. Like
    Hany Salah got a reaction from amitk3553 in Polymorphism in testbench   
    in case you have such ubus example,,, you have different agents ,, each one is responsible to act like either master or slave ,, It isn't restricted that all agents act in the same way at the same time,, but you have to randomly configure each one to make your test more random and more effective ,, such way ,, you have different agents ,,, each one extended from uvm_agent base class ,, and each one may have the same function name ,, for instance write(),, strope () ,, read() and so on ,, 
     
    Through build phase ,, you called build function through all environments in the same test bench ,, although they have the same name ,, polymorphism play its role 
     
    another example through when run phase ,,, each agent may have his own run routine with the same name run () ,, but they don't act as each other ,, so polymorphism play its role here also 
     
    on Other matter ,, naming function whose main purpose similar like run, is so practical as on complex tests you have high number of agents and scripts and you may get lost in routines' names  
  2. Like
    Hany Salah reacted to apfitch in Confused between Definitions   
    Hi Hany,
     just returning to your original question yes you can have two analysis *ports* in a class. However as David explained, there is a problem if you try to have two analysis *imp*s in a class. Because then you need two functions called write() (the function implementations), which only differ in argument type - which is not allowed.
     
    What the decl_imp macros do is declare a kind of wrapper class, which implements write(), and then automatically forwards write to a function with a different name. You can then write the two functions with different names as that doesn't require overloading.
     
    You might find it helpful to look at the macro itself to see exactly what it does,
     
    regards
    Alan
  3. Like
    Hany Salah reacted to David Black in Confused between Definitions   
    SystemVerilog does not allow 'function overloading' like C++. Suppose I have a class A with a function write as follows:
     
    class MyClass
        function void write(input T1 value); ... endfunction
        function void write(input T2 value); ... endfunction // ***ERROR*** Not allowed to have two 'write' functions in same class (no overloading allowed)
       ...
      Instead you should have:
     
    class MyClass
        function void write_T1(input T1 value); ... endfunction
        function void write_T2(input T2 value); ... endfunction // OK, different name
       ...
  4. Like
    Hany Salah reacted to dave_59 in UVM in Questasim   
    I answered this here.
  5. Like
    Hany Salah reacted to apfitch in Randomization in Configuration Classes   
    No, configuration could be used to set up a sequence, for instance, and then by randomizing the configuration you could get different sequences.
     
    A simple example would be a sequence to read and write from a start address to an end address. You could put the start address and the end address in a configuration object as rand variables with constraints; and then randomize the configuration to get different ranges of addresses.
     
    Of course in that example, it would probably be easier to make the rand variables members of the sequence, but for more complex configurations it could well make sense to have a configuration object.
     
    regards
    Alan
  6. Like
    Hany Salah reacted to apfitch in Randomization in Configuration Classes   
    I assume when you say "set rand variables" you mean "declare rand variables"?
     
    You put rand variables in a configuration class so you can randomize the configuration,
     
    regards
    Alan
  7. Like
    Hany Salah reacted to apfitch in Confused between Definitions   
    I don't believe there is a difference, though I'm happy to be corrected.
    UVC seems to be the preferred terminology of Cadence.
     
    regards
    Alan
  8. Like
    Hany Salah reacted to xiaodong.zhuang in Confused between Definitions   
    Per my understanding, UVC can be two types, module UVC and interface UVC, module UVC is usually passive for checkers/monitors/scoreboards of a DUT, and interface UVC is usually active for stimulus driving. And for agent, usually a UVC can have several agents inside, for example, a AHB UVC can have master agent and slave agent both inside.
     
    Hope that be helpful.
  9. Like
    Hany Salah reacted to kansagaratushar in Inquiry in UVM   
    HI,
     
    It  indicates TLM port declaration,
    Here "uvm_blocking_get_port"  is TLM and used to communicate with other block.
    "Simple_trans" is data type of communication.
    get_port is substantiation,
     
    For more Details Refer http://testbench.in/UT_13_UVM_TLM_1.html
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