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zhiharev

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zhiharev last won the day on December 23 2015

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  1. I don't think that the problem is about item_done() after stop_sequences(). When this happens we get another message.
  2. I have a reset sequence, which starts as default_sequence for reset_phase. For main_phase I have some sequence, which is started as default sequence. At some time I jump from main_phase to reset_phase. Then I get error: [sEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.ctb_agent.sequencer' for sequence 'default_parent_seq' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues This error occures only if at the moment of the jump has_do_avaliable() of ctb_agent.sequencer returns 1'b1. Why does it happen? I believe that jumping to another phase doesn't kill sequences.
  3. For this comment, I think we can try to make it this way: // ----------------------------------------- // Real DUT register // way field controls which data register // will be ascessed // ------------------------------------------ class ctrl_reg extends uvm_reg; uvm_reg_field some_field; uvm_reg_field way; // if 0, access to data0 reg, if 1, access to data1 reg endclass // ----------------------------------------- // Virtual register, idx field is a handle // to way field of ctrl_reg // ------------------------------------------ class idx_reg extends uvm_reg; uvm_reg_field idx; endclass // ----------------------------------------- // data0 and data1 share the same physical // address // ------------------------------------------ class data0_reg extends uvm_reg; uvm_reg_field field0; endclass class data1_reg extends uvm_reg; uvm_reg_field field0; uvm_reg_field field1; endclass // ----------------------------------------- // Indirect register for accesing data0 and // data1 registers. // The number of bits in each register in // the register array must be equal to n_bits // of this register. // ------------------------------------------ class data_reg extends uvm_reg_indirect_data; // No fields endclass class reg_model extends uvm_reg_block; ctrl_reg ctrl; idx_reg idx; data0_reg data0; data1_reg data1; data_reg data; uvm_reg reg_ar[]; virtual function build(); reg_ar = new[2]; data0 = data0_reg::type_id::create(); data0.configure(this); data.build(); data1 = data1_reg::type_id::create(); data1.configure(this); data.build(); reg_ar[0] = data0; reg_ar[1] = data1; ctrl = ctrl_reg::type_id::create(); ctrl.configure(this); ctrl.build(); idx = idx_reg::type_id::create(); idx.configure(this); idx.build(); idx.idx = ctrl.way; data = data_reg::type_id::create(); data.configure(idx, reg_ar, this, null); data.build(); default_map = create_map(““, 0, 4, UVM_BIG_ENDIAN); default_map.add_reg(ctrl, 0); default_map.add_reg(data, 4); endfunction endclass P.S. this is just concept
  4. I have DUT which contains 2 registers ( A and B ) with the same addres. DUT also has the third register ( C ) which control to what register write: to A or to B. Using RAL we have problems with mirroring registers A and B, because they have the same physical addres. How caw we solve it? I found a way which works: 1) give registers A and B unique addresses 2) make register adapter to change address using register C
  5. uvm_analysis_imp #(REQ, l3_ack_sequencer #(REQ)) generate_res; This solved the problem, thank you. I, really, forgot about declaring the parameter for the imp.
  6. I have a sequencer: class l3_ack_sequencer #(type REQ = uvm_sequence_item) extends uvm_sequencer #(REQ); `uvm_component_utils_begin(l3_ack_sequencer#(REQ)) `uvm_component_utils_end uvm_analysis_imp #(REQ, l3_ack_sequencer) generate_res; function new (string name, uvm_component parent); super.new(name, parent); generate_res = new("generate_ack", this); endfunction virtual function void build_phase(uvm_phase phase); super.build_phase(phase); endfunction virtual function void connect_phase(uvm_phase phase); super.connect_phase(phase); endfunction // Generate ack virtual function void write(REQ item); endfunction endclass Then I declare a handle somewhere: l3_ack_sequencer #(core_l3q_ireq_tran) l3r_ireq; Using Synopsys VCS I have an error: Error-[iCTTFC] Incompatible complex type usage .../l3_ack_sequencer.sv, 33 Incompatible complex type usage in task or function call. The following expression is incompatible with the formal parameter of the function. The type of the actual is 'class $unit::l3_ack_sequencer#(class $unit::core_l3q_ireq_tran)', while the type of the formal is 'class $unit::l3_ack_sequencer#(class uvm_pkg::uvm_sequence_item)'. Expression: this Source info: uvm_analysis_imp_8::new("generate_ack", this) Can anyone help me to solve this problem or explain why it cant be solved?
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