Roman Popov

Members
  • Content count

    95
  • Joined

  • Last visited

Everything posted by Roman Popov

  1. Hello, All the answers can be found in standard: http://standards.ieee.org/getieee/1666/download/1666-2011.pdf Questions are tricky, so it's hard to guess answers without reading documentation carefully. Especially: Afaik, standard does not prohibit running processes in parallel, in case it is invisible to user. So implementation of standard can run some processes in parallel. But Accellera opensource SystemC implementation is single-threaded.
  2. Yes, I do this kind of conversion of TLM-1.0 to TLM-2.0 and vice versa very often, because for synthesis only TLM-1.0 is supported, and for VP TLM-2.0 is commonly used. The converter will be application-specific, because TLM-1.0 has no standard payload (Many TLM-1.0 models even define their own interfaces, instead of using standard put/get ).
  3. I've needed it for test environment modeling purposes, not for synthesis. Delta delay problems (also known as Shoot-thru) are possible in synthesizable SystemC. Common case is when you have a clock gate that inserts a delta delay into a clock signal distribution network. However in SystemC it is solved in a different way: Instead of delaying all assignments, you use immediate notifications inside clock signal, so that processes sensitive to gated clock are executed in the same delta cycle with processes sensitive to ungated clock.
  4. Hello, I need to port following code from Verilog to SystemC: assign #DELAY out = in; What is the best known method to do this in SystemC? Similar question on stackoverlow https://stackoverflow.com/questions/5566785/specifying-signal-delays-in-systemc-as-clause-after-in-vhdl
  5. -isystem libs/systemc-2.3.1a/include This line looks suspicious. Should not it be something like -I/path/to/systemc/include ?
  6. Well, it's not compiling because con_arrayfifo is not a member of arrayfifo... You should declare it as a method in class body.
  7. In general google test was not designed for hardware verification, probably you should better look on UVM-SystemC when it will be released.
  8. Do you create a separate executable for individual test? More related discussions here: https://stackoverflow.com/questions/43145530/does-systemc-unit-testing-need-forking https://stackoverflow.com/questions/4923292/using-existing-unit-test-frameworks-with-systemc
  9. Here is an example of connecting serial port model to TCP socket: https://git.greensocs.com/models/tcp_serial
  10. Runs without any issues on Linux: 0 s s: true 0 s i: true 50 ms s: false ... 950 ms s: false Unfortunately I have no Windows machine near me to check with MSVC.
  11. Compiles without any warnings in G++4.8.
  12. Class Top is not declared/defined
  13. detect.h source code is not included, so I can't compile this.
  14. Unfortunately being a hardware developer you are doomed to suffer. You should either accept it, or quit :) EDA vendors assume that you will be using SystemC as a part of some commercial simulation or synthesis tool, and Red Hat 6 is the only supported platform in general.
  15. Hello, Is it possible to install two builds of SystemC (-DCMAKE_BUILD_TYPE=Release and -DCMAKE_BUILD_TYPE=Debug) simultaneously into a filesystem? So that find_package(SystemCLanguage) will link one of two, depending on CMAKE_BUILD_TYPE of application? (I know that there is a RelWithDebInfo option that tries to serve both release and debug purposes, but it does not work really well for debug because of enabled optimizations)
  16. Yes, both are just C++ libraries.
  17. If you are using CMake build, then just pass -DBUILD_EXAMPLES=ON and all bundled examples will be built. Including risc_cpu example. You can run examples using general CTest flow (check documentation on cmake website https://cmake.org/Wiki/CMake/Testing_With_CTest )
  18. No, multiple inheritance is not supported in this case Here is quote from IEEE 1666-2011 So you have two options: Use composition instead of inheritance : in SystemC case this means you need to instantiate modules and bind their ports In some cases you can put some sc_objects in pure C++ classes (not sc_modules). This technique is commonly used for "port bundles". For example: struct clock_reset_if { sc_in_clk clk{"clk"}; sc_in<bool> rstn{"rstn"}; } struct some_module: sc_module, clock_reset_if { // ... } Unfortunately this approach does not work with SC_METHOD/SC_THREAD macros. But I think it should work with sc_spawn.
  19. It turned out you need not to modify anything in CMake scripts. There is a "secret" option -DCMAKE_DEBUG_POSTFIX . Here is the procedure: 1) Build and install SystemC in Debug mode: mkdir build_debug && cd build_debug cmake ../ -DCMAKE_CXX_STANDARD=11 -DCMAKE_BUILD_TYPE=Debug -DCMAKE_DEBUG_POSTFIX=d make sudo make install 2) Build and install SystemC in Release mode: mkdir build_rel && cd build_rel cmake ../ -DCMAKE_CXX_STANDARD=11 -DCMAKE_BUILD_TYPE=Release make sudo make install 3) Now you have both debug and release library installed in /opt/systemc : ls -l /opt/systemc/lib/ total 14608 drwxr-xr-x 4 root root 4096 Jun 14 09:08 cmake lrwxrwxrwx 1 root root 18 Jun 14 09:08 libsystemcd.so -> libsystemcd.so.2.3 lrwxrwxrwx 1 root root 37 Jun 14 09:08 libsystemcd.so.2.3 -> libsystemcd.so.2.3.2_pub_rev_20170606 -rw-r--r-- 1 root root 12751464 Jun 14 09:08 libsystemcd.so.2.3.2_pub_rev_20170606 lrwxrwxrwx 1 root root 17 Jun 14 09:12 libsystemc.so -> libsystemc.so.2.3 lrwxrwxrwx 1 root root 36 Jun 14 09:12 libsystemc.so.2.3 -> libsystemc.so.2.3.2_pub_rev_20170606 -rw-r--r-- 1 root root 2196784 Jun 14 09:12 libsystemc.so.2.3.2_pub_rev_20170606 4) Application project will pick required library automatically depending on CMAKE_BUILD_TYPE. Here is example CMakeLists.txt : find_package(SystemCLanguage CONFIG REQUIRED) add_definitions(-DSC_INCLUDE_DYNAMIC_PROCESSES) set (CMAKE_CXX_STANDARD ${SystemC_CXX_STANDARD} ) set(SOURCE_FILES main.cpp) add_executable(sysc_example ${SOURCE_FILES}) target_link_libraries(sysc_example SystemC::systemc)
  20. You see at least two bugs in your code: for (int i = 0; i < N; i++){ SM[i].i_clk(i_clk); SM[i].i_rst(i_rst); SM[i].i_en(s_en); SM[i].o_finish(s_finish[i]); SM[i].o_data(o_data[i]); // <<< here you forgot subscript operator : SM[i].o_data[i](o_data[i]); } I also recommend to use .at(N) instead of [N] during elaboration since it does bounds checking. Performance is not an issue during elaboration, since it is done once. In a TOPMODULE you've forgotten to initialize o_data sc_vector< sc_out<uint_16b> > o_data; // Not initialized in TOPMODULE constructor If you can use C++11, I recommend using in-class initializers, since they are more readable, like : ... sc_in_clk i_clk {"i_clk"}; sc_in<bool> i_rst {"i_rst"}; sc_in<uint_8b> i_type {"i_type"}; sc_vector< sc_out<uint_16b> > o_data {"o_data", N}; ...
  21. I would advice using SC_CTHREADS both for DUT and Testbench when debugging signal-level protocols. This will save you from race conditions (everything will be synchronized to common clock signal) This particular protocol is implemented inside SystemC examples, you can check usage example in systemc_root/examples/sysc/2.3/sc_rvd/*
  22. Thanks! I was not aware of sc_event_queue and even started writing something similar from scratch :)
  23. The only supported standard channel for synthesis in modern HLS tools is sc_signal. It is pretty low-level. Unfortunately, other high-level communication components are vendor-specific.
  24. It is possible if you know expected template parameters in advance. http://en.cppreference.com/w/cpp/language/class_template#Explicit_instantiation This technique is quite often applied in mathematical libraries to reduce compile time.
  25. Hi, you can debug segmentation fault with debugger. Most likely you have some typo with implicit cast in your program. Fortunately segfaults are easy to debug!