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Roman Popov

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Roman Popov last won the day on October 19

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About Roman Popov

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  1. Roman Popov

    tlm_fifo nb_peek

    2.3.3 will be released next week w/o a fix. So most likely next one after 2.3.3
  2. Those questions are covered in detail in paragraphs 14.1 and 14.2 of SystemC standard. Can't answer in a better way. TLM2.0 simulations are not cycle-accurate, so you don't have clock edge events. In AT modeling style you should call wait(delay) after each transport call. In LT modeling style all initiators are temporaly decoupled and can run ahead of simulation time, usually for a globally specified time quantum. For debugging you can use the same techinques as in cycle-accurate modeling: Source-level debugging with breakpoints and stepping Transaction and signal tracing Logging Comparing with RTL, debugging using waveform won't be that effective, because in AT/LT modeling state of model can change significantly in a single simulator/waveform step. Usually preffered way is combination of logging and source-level debug. Debugging TLM models is harder comparing to RTL. Also C++ is much more complex and error-prone comparing to VHDL/Verilog.
  3. TLM payload is used for untyped raw data transfers. Data format is usually a property of device. Let's consider an example: Initiator is CPU model, and target is Convolution filter accelerator. Accelerator accepts a 2d matrix (2d array) of coefficients as an input. Documentation of accelerator must specify a binary format of data, for example: coefficients are stored in row-major order, each coefficient is 8-byte signed integer. Using this documentation initiator converts 2d array into a raw data of tlm payload. And device model converts raw data back into 2d array. This is how it is usually done.
  4. Roman Popov

    tlm_fifo nb_peek

    Thanks for report. I will put this into SystemC bug tracker. Until it is fixed, you can use a workaround: target_port->tlm_get_peek_if<int>::nb_peek(b);
  5. Hi johnmac, What you try to do is conceptually wrong: Ready and Valid should be two separate signals. Initiator drives the Valid signal, and responder drives the Ready. There is an example of ready-valid channel that comes together with SystemC, check in systemc/examples/sysc/2.3/sc_rvd If your final goal is synthesizable code, then both Mentor and Cadence synthesis tools already have it implemented in their libraries. Check vendor documentation. If you still want to simulate your design, you can try to use SC_UNCHECKED_WRITERS instead of SC_MANY_WRITERS. This will disable a check for multiple drivers in a single delta cycle.
  6. Hard to say something without a complete source code. The purpose of TLM-2.0 standard is model interoperability. So that TLM model developed by one vendor can be used in VP developed by other vendor. Building systems using low-level TLM-2.0 APIs can be quite hard. For device and system modeling you should probably use some high-level framework built on-top of TLM-2.0 standard. If you look for something open-source try to check GreenLib https://www.greensocs.com/docs , or SCML https://www.synopsys.com/cgi-bin/slcw/kits/reg.cgi . Large semiconductor vendors can have proprietary TLM frameworks, so check if there is one developed inside your company.
  7. Roman Popov

    using gtkwave

    No. If you want to model a gate with a delay to output you will need to attach a delay line (check AmeyaVS code on a thread I've referenced before) to output signal. But first I suggest you to learn what each line in your code does, and understand why it does not work.
  8. Roman Popov

    using gtkwave

    I don't work on Windows. But as far as I remember executable should be somewhere in project sub-directory called "Release" or "Debug". Sorry, can't help you more here.
  9. Roman Popov

    using gtkwave

    In the working directory (active directory when you launch the executable). Search for "and_gate.vcd"
  10. Roman Popov

    using gtkwave

    I've removed next_trigger and simulated your code. Check attached waveform. Check how to model delay line here:
  11. If by queue you mean payload event queue ( peq_with_cb_and_phase or peq_with_get), then it's purpose is to sort transactions based on delay annotation. Considering your example with two transactions: suppose you recieved 1st transaction with delay 40ns, and 2nd with delay 10 ns. Then you have to process 2nd transaction before 1st. Payload event queue may help with this.
  12. Roman Popov

    using gtkwave

    Your code is not correct. Why did you put next_trigger(5, SC_NS) inside a method? Remove it, and you will get correct waveform for and gate.
  13. Consider for example modern bus protocols like AMBA-AXI with out-of-order transaction termination. 2nd transaction can terminate before 1st in this case. It is not possible to model this with a single b_transport call. I think AT modeling was designed for such cases.
  14. Roman Popov

    SystemC 2.3 Pretty-Printer

    Hard to say without debugging. In source code I see they are registered using "RegexpCollectionPrettyPrinter", probably sc_dt::sc_int<(.*)> matches sc_signal<sc_int<2>> ? By curiosity, may I know how you manage signals/ports? Signal has m_cur_val and m_new_val fields, storing current and next signal value. So they are pretty-printed as "m_cur_val -> m_new_val". Ports are just decorated pointers, signal port has m_interface field holding a pointer to signal, so pretty-printer dereferences it, casts to dynamic type and prints it the same way as signal. Actually you can do much more with GDB Python API. I have even written SystemC to Verilog converter using GDB (Generates complete netlist, but without process bodies). Commercial SystemC interactive simulators/debuggers are also based on GDB AFAIK.
  15. Roman Popov

    SystemC 2.3 Pretty-Printer

    I'm not using this particular pretty-printer, since we have a better one internally. But simply by looking at source code, it seems like it does not supports signals/ports: https://github.com/AHeimberger/SystemC-2.3-Pretty-Printer/blob/master/systemc23/systemc23printers.py