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Roman Popov

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Roman Popov last won the day on August 14

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About Roman Popov

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  1. You have controversial requirements: a) put stored value when enable == 1 , which sounds like a dff with output_enable b) put input to output when enable == 1, which sounds more like a latch Anyway, in both cases you will need to make process sensitive to enable signal. And usually such low-level logic is modeled with SC_METHODs. In SystemC context "register" usually means some memory-mapped CSR on TLM bus 🙂
  2. What do you mean exactly by "modeling a register"? If you are working on synthesizable code (i.e. using Mentor/Cadence HLS tools), then it is not possible to have 0-delay communication between threads in synthesizable code, as you wanted in original post. At least it was not possible last time I've used these tools. If you are working on some non-synthesizable high-level model, then you can model "register" any way you like, you don't even have to use sc_signal<> for that purpose.
  3. If you want immediate communications between threads, then you should use regular SC_THREADs and wait on event, like wait(some_signal.value_changed_event());
  4. You have 2 clocked processes. Any communication between them will take at least 1 clock cycle. If you need request and response, then you have at least 2 cycle latency.
  5. Roman Popov

    sc_trace for sc_bigint<W> when W=1024

    There is a buffer overflow bug in vcd_sc_signed_trace::write, someone forgot to reserve a space for null terminator in null-terminated string. void vcd_sc_signed_trace::write(FILE* f) { static std::vector<char> compdata(1024), rawdata(1024); typedef std::vector<char>::size_type size_t; if ( compdata.size() < static_cast<size_t>(object.length()) ) { size_t sz = ( static_cast<size_t>(object.length()) + 4096 ) & (~static_cast<size_t>(4096-1)); std::vector<char>( sz ).swap( compdata ); // resize without copying values std::vector<char>( sz ).swap( rawdata ); } char *rawdata_ptr = &rawdata[0]; for (int bitindex = object.length() - 1; bitindex >= 0; --bitindex) { *rawdata_ptr++ = "01"[object[bitindex].to_bool()]; } *rawdata_ptr = '\0'; compose_data_line(&rawdata[0], &compdata[0]); std::fputs(&compdata[0], f); old_value = object; } When you have sc_bigint<1024> , 1024 chars in compdata and rawdata are not enough to store 1024 symbols, because 1 symbol is required for null terminator assigned here: *rawdata_ptr = '\0'; It will also fail with sc_bigint<4096> Can you add + 1 to size of buffer everywhere , rebuild SystemC and rerun your test? : void vcd_sc_signed_trace::write(FILE* f) { static std::vector<char> compdata(1024 + 1), rawdata(1024 + 1); typedef std::vector<char>::size_type size_t; if ( compdata.size() < static_cast<size_t>(object.length()) ) { size_t sz = ( static_cast<size_t>(object.length()) + 4096 ) & (~static_cast<size_t>(4096-1)); sz ++; ... Same problem also with sc_biguint<1024>. Thanks for finding this bug!
  6. Roman Popov

    sc_trace for sc_bigint<W> when W=1024

    Thanks for reporting this. I've reproduced the issue. On my side (VS 2017) it crashes with heap corruption, instead of hanging. But I think this is the same issue. I will debug on this evening.
  7. Roman Popov

    sc_trace for sc_bigint<W> when W=1024

    I can't reproduce, works fine for sc_bigint<1024> on my side. What compiler and OS do you use?
  8. Roman Popov

    sc_vector of modules with paramterized constructors

    In a current SystemC releases you will have to use Creator (check SystemC standard), that will generate arguments for each element constructor. Quite inconvenient. In next SystemC release sc_vector will have emplace_back() method.
  9. Roman Popov

    find parent port?

    I had the same problem when working on connection visualization tool for SystemC, had to hack SystemC kernel to preserve port-to-port connections after elaboration. What I've found that in many real models some ports are connected through hierarchical boundaries like: input_port.bind ( mod.submod.other_submod.channel ) So I also had to create "virtual" ports, that do not exist in code, just for visualization.
  10. Roman Popov

    Initial value port

    I always change default policy to SC_MANY_WRITERS. In commercial simulators usually there is also a way to change default policy. In verification environments default SC_ONE_WRITER policy is violated way too often. It also does not work well with FORK/JOIN, when you spawn different threads in each test to generate stimulus on same set of ports.
  11. This is not official Accellera repository. But in case your company is Accellera member you can request access to Accellera UVM git repositories.
  12. Independently on thread evaluation order code will output 0x0. Because signal values are updated during "Update phase" of simulation. Check Section "4. Elaboration and simulation semantics" of SystemC standard.
  13. Roman Popov

    Modeling large memories in System-C

    You can start with std::unordered_map<address_t, data_t> and later switch to "paged" solution as swami suggested if performance of unordered_map is not sufficient for your case.
  14. Roman Popov

    reading part of input port

    Well, sc_int also support range access, so you could do the same in original code.
  15. Not possible with sc_clock. You will have to write your own clock generating class. This is what we've done in similar case.
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