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  1. Connect SystemC to Linux Ethernet Socket

    Thank you, I needed a UDP socket but I succeeded making an interface based on boost::thread and boost::mutex as described in the TCP serial model. It seems that it's not very fast, but it's much better and good enough for my needs. Regards, Mathieu
  2. Hi, I need to make a connection between my SystemC design and an Ethernet socket (on Linux). It seems possible as described in this project : https://github.com/dcblack/technology_demonstrator from David Black which "ties a zedboard design to a SystemC ESL design". Unfortunately some files are missing in the previous repo (linked to a dropbox folder). Does anybody know how to do it ? David, I would really appreciate some help :) Thanks, Mathieu
  3. Maximum number of SC_MODULE ?

    Great, thank you so much Alan ! This was exactly the cause of my problem. I changed the stacksize and it's running fine. Thanks for the pointer solution, I will think about it (hoping it's well supported by the synthesis tool). I wasn't familiar at all with the stack/heap aspect. I searched for hours, I would never have found. Thanks again for your help. Regards, Mathieu
  4. Hi, I have an error at runtime that says "in sc_main (argc = Cannot access memory at address 0x....)" I use system 2.2.0 on a 64 bit linux machine. The problem appears when I try to instanciate 1100 additional sc_modules in my design. I was wondering : is there a maximum number of SC_MODULE ? Or if someone has any idea about the cause of the problem it would be really great... Thanks, Mathieu
  5. sc_report_handler

    Hi, Do you know where I can find some examples about the sc_report_handler ? I would like to know the possibilities offered by this class. Thanks, Mathieu
  6. synthesizeable systemc code

    Ok sorry I wasn't clear : - you can use your class as you want, you don't have to change anything - but if you want to write your digit object to a channel (ex : sc_fifo), it seems to me that you must be able to convert your class to a vector For example (with 2 data members) : class digit { public: sc_int<4> dt1; sc_int<4> dt2; //... }; inline void type_to_vector(const digit & in, int length, sc_lv<8> & rvec) { rvec.range(7,4) = in.dt1; rvec.range(3,0) = in.dt2; } inline void vector_to_type(const sc_lv<8> & in, bool issigned, digit * result) { sc_biguint<8> tmp = in; result->dt1 = tmp.range(7,4); result->dt2 = tmp.range(3,0); } This code is synthesizable. Maybe this is not exactly your question, I just pointed this because you don't have this kind of constraint in C++. Mathieu
  7. synthesizeable systemc code

    Hi, My experience is that you can synthesize your code if your data type can be converted to a vector (sc_lv) : that is to say data class members are concatenated to a vector. You need to make 2 conversions functions (type_to_vector and vector_to_type) to do this. I don't know any free tool for systemc synthesis (I use catapultc from calypto which is very powerfull but expensive). If you use xilinx, it seems vivado now includes high level synthesis for C/C++/SystemC. Regards, Mathieu
  8. SystemC generator

    Hi all, I am looking for a tool (preferably open souce) to convert a schematic into systemc (empty modules and interconnections). Do you know a soft that can do that ? Thanks!