[Package for parametric design]

Hi,

I need to design & verify parametric design, such that my design & verif env will be instantiated twice, each time with different parameters.

I usually work with packages for my design, so all of parameters, structs etc are defined there.

My questions:

Is there a  way to write such package so same package will hold same parameter  with two different values? (different value for each instance)

Is there a robust way in uvm to verify such design?

Thanks!

[parsing using system verilog]

Hi,

I have an IP with built in tests, written in pyhton.

I want to parse those tests and use them in higher level (uvm testbench). Eventually each test will be a uvm sequence.

For that I need a system verilog parser.

Is there a reference that I can use for this purpose?

example for lines in existing test:

 

WriteBlock SLAVE 0x0000ffff

Data 8

a5a5a5a5 ffffffff 

 

Thanks