You're correct that PSS is intended for hardware verification -- specifically targeted at the transaction and higher level of abstraction. 4-state modeling typically applies at the signal level, and doesn't propagate up to transaction level and above. I double-checked, and the SystemVerilog LRM specifically restricts randomization to 2-state values: "Constraints support only 2-state values. The 4-state values (X or Z) or 4-state operators (e.g., ===, !== ) are illegal and shall result in an error." Hope this helps!
Hello Raj, Many thanks for your review comments in the grammar and examples! Your comments regarding unused terminals (issues 2, 4, 5, 6, 12, 13, 14) make perfect sense, and I'll proceed to file Mantis items for these. I will need to investigate a bit more on the issues you point out with respect to items that appear incorrectly grouped, but will also develop proposals to add to Mantis items for these as well. Best Regards, Matthew