milind.shende5

Thanks to Alan and Karandeep for your elaborate replies. Now the things are much clearer to me. so If I have to define a clock, it should be sc_clock clk1(clk1, double_value_period, Time_unit_in_capital, duty_cycle, time_offset, first edge true/false);

Thanks for the replies. in SystemC Version 2.0 User's Guide, on page 80, the description about Clock is given. In the example on the same page, the clock is defined as follows sc_clock ck1("ck1", 20, 0.5, 0, true); It states in the description that "This declaration will create a clock object named clock with a period of 20 time units, a duty cycle of 50%, the first edge will occur at 2 time units, and the first value will be true." In the given example, the time resolution is not specified, that means as per the IEEE std 1666-2011, page 102, the default time resolution is 1 ns and above clock declaration has clock period of 20 ns. is this correct ? and if I want to set other clock period, I have two options 1st Option: sc_clock clk1(clk1, 20, SC_US, 0.5, 0, true); 2nd Option: define time resolution in constructor before clock definition sc_set_time_resolution (1.0, SC_US); and then define the clock as sc_clock clk1(clk1, 20, 0.5, 0, true); what you say, is this correct? thanks, Milind.

Hello All, this could be very primitive question, but haunts me from some time. what is default time unit in systemC and how it can be set ? In case of setting clock in the top level module, the clock period can be defined using number of time steps, But I don't know what is the time unit of my module. Where the default time unit can be seen ??? I also want to know this for using advanced simulation controls. thanks in advance, regards, Milind

Hello Bogdan, while searching for the missing file in the referenced book, and on this current discussion forum, I got directed to following link by my google browser, which is nothing but a old discussed initiated by the Author of the book himself. http://www.accellera.org/Discussion_Forums/ams_forum/archive/msg?list_name=ams_forum&monthdir=201106&msg=msg00015.html in this link you can see the attachment testcode.tgz. by downloading and uncompressing the attachment, you may get the required files. all the best. regards, Milind.

Hello All, Can we use "while loops" in SystemC-AMS constructs (TDF modeling) ? Can somebody refer a tutorial or a reference code which uses while loop in SC-AMS. thanks, Milind.

Hello All, I am modeling A2D that uses a successive approximation algorithm. I have modeled A2D converter in SystemC and SystemC-AMS. But both of the models give me some errors. SC model ends up with infinite loop, and SC-AMS model ends with segmentation fault the models are as follows: SC models: Location of the while loop could be the serious problem. I have tried changing the location in side switch statement, but error persists. //error message: stage 1: start edge stage 1: start edge stage 1: start edge stage 1: start edge stage 1: start edge stage 1: start edge stage 1: start edge ...... infinite loop // SC_A2D.h #include<systemc.h> enum adc_state {input, convert}; SC_MODULE(A2D_module) { sc_in_clk clk; sc_in_clk start; sc_in<double> ain; sc_out<sc_logic> eoc; sc_out<sc_lv<8> > dout; sc_signal <adc_state> status; void conversion_logic(); // void next_state_logic(); SC_CTOR(A2D_module) { SC_CTHREAD(conversion_logic, start.pos()); } }; //SC_A2D.cpp #include <SC_A2D.h> void A2D_module::conversion_logic() { eoc = SC_LOGIC_0; dout = "00000000"; double thresh, Vtemp; sc_lv<8> dtemp; int bit_cnt = 8; status = input; while(bit_cnt > 0) { switch (status){ cout << "begin !!!"; case input: if (start == 1) { cout << "stage 1: start edge" << endl; thresh = 5.0; Vtemp = ain; eoc = SC_LOGIC_0; status = convert; } break; case convert: if (clk == 1) { cout << "stage 2: clk edge" << endl; thresh = thresh/2.0; if (Vtemp > thresh) { cout << "stage 3: Vtemp > thresh" << endl; dtemp[bit_cnt]= '1'; Vtemp = Vtemp- thresh; } else { dtemp[bit_cnt]= '0'; } if (bit_cnt > 0) { cout << "stage 4: bit_cnt > 0" << endl; bit_cnt = bit_cnt - 1; } else { cout << "last stage: conversion" << endl; dout = dtemp; status = input; wait(10, SC_US); eoc = SC_LOGIC_1; } } break; } // end switch } // end while } // end method conversion_logic ------------------------------------------------------------------------------------------------------------- SC-AMS models: which gives segmentation fault // Error message: stage 1: Read Input stage 3: Convert Input stage 1: Read Input stage 2 : start edge stage 3: Convert Input stage 4: clk edge !!! bit_cnt = 7 stage 1: Read Input stage 3: Convert Input stage 1: Read Input stage 3: Convert Input stage 4: clk edge !!! Segmentation fault // A2D.h #include <systemc-ams> #include <systemc> #include <stdio.h> using namespace std; //ref: VHDL-AMS Model of A2D converter given in System designer's guide to VHDL-AMS on page 287 SCA_TDF_MODULE (a2d_nbit) { //port declaration sca_tdf::sca_in<double> ain; // analog input pin sca_tdf::sca_de::sca_in<bool> clk; //clock signal sca_tdf::sca_de::sca_in<bool> start; //clock signal sca_tdf::sca_de::sca_out<sc_dt::sc_logic> eoc; //end of conversion pin sca_tdf::sca_de::sca_out<sc_dt::sc_lv<8> > dout; //digitalized output a2d_nbit(sc_core::sc_module_name nm, double Vmax_ = 5.0, double delay_ = 10.0e-6, int bit_range_ = 8, bool start_x_ = 0, bool clk_x_ = 0): ain("ain"), start("start"),clk("clk"), eoc("eoc"), dout("dout"), Vmax(Vmax_), delay(delay_), bit_range(bit_range_), start_x(start_x_), clk_x(clk_x_){} void set_attributes() { set_timestep(50, sc_core::SC_US); eoc.set_delay(1); } void initialize() { eoc.initialize(sc_dt::SC_LOGIC_0); } void processing(); private: double delay; // ADC conversion time double Vmax; int bit_range; bool clk_x; bool start_x; }; // A2D.cpp void a2d_nbit :: processing() { // double Vin = ain.read(); double thresh; //Threshold to test input voltage double Vtemp; //snapshot of input voltage when conversion starts sc_dt::sc_lv<8> dtemp; //temparary output data enum state {input, convert}; int bit_cnt; state status = input; switch(status) // ref: systemC state machine example in SystemC user guide on page 171 { case input : cout << "stage 1: Read Input" << endl; if((start == true) && (start_x == false)) //if (start == true) { cout << "stage 2 : start edge" << endl; bit_cnt = bit_range; thresh = Vmax; Vtemp = ain; eoc = sc_dt::sc_logic('0'); } case convert: cout << "stage 3: Convert Input" << endl; if ((clk == true) && (clk_x == false)) //if (clk == true) { cout << "stage 4: clk edge !!!" << endl; thresh = thresh/2.0; if (Vtemp > thresh) { dtemp[bit_cnt]= '1'; Vtemp = Vtemp - thresh; } else { dtemp[bit_cnt]= '0'; } if (bit_cnt > 0) { bit_cnt = bit_cnt - 1; cout << " bit_cnt = " << bit_cnt << endl; } else { dout = dtemp; eoc = sc_dt::sc_logic('1'); status = input; } break; } default: break; } // end switch start_x = start; clk_x = clk; } ---------------------------------------------------------------------------------------------------------------- // voltage source: dummy_source.h #include<systemc-ams> #include<systemc> #include<iostream.h> #include<fstream.h> using namespace std; SCA_TDF_MODULE (dummy_src) { // sca_tdf::sca_de::sca_out<double> output; sca_tdf:: sca_out<double> output; ifstream infile; double val; dummy_src(sc_core::sc_module_name): output("output"){} void set_attributes() { set_timestep(50, sc_core::SC_US); infile.open("datalog.txt"); } void processing () { if (infile >> val) { output.write(val); } else { output.write(0.0); } } }; ------------------------------------------------------------------------------------------------------------- // top_level_entity : interface.h #include<systemc-ams> #include<systemc> #include<A2D.h> //#include<SC_A2D.h> #include<dummy_source.h> using namespace std; using namespace sc_core; SC_MODULE (interface2) { // A2D_module a2d; a2d_nbit a2d; dummy_src input_vtg; sc_core::sc_clock clk1; sc_core::sc_clock start1; SC_CTOR(interface2) :in("in"), out("out"), a2d("a2d"), input_vtg("input_vtg"), clk1("clk1", 100, sc_core::SC_US, 0.5), start1("start1", 200, sc_core::SC_US, 0.5), eoc("eoc") { input_vtg.output(in); a2d.ain(in); a2d.start(start1.signal()); a2d.clk(clk1.signal()); a2d.eoc(eoc); a2d.dout(out); } public: // sc_core::sc_signal <double> in; sca_tdf::sca_signal<double> in; sc_core::sc_signal<sc_dt::sc_lv<8> > out; sc_core::sc_signal<sc_logic> eoc; }; // top_level_entity: interface2.cpp #include<systemc-ams.h> #include<systemc.h> #include<iomanip> #include<interface2.h> int sc_main(int argc, char* argv[]) { interface2 if2_dut("if2_dut"); sca_util :: sca_trace_file* atfs = sca_util :: sca_create_tabular_trace_file("if2.dat"); sca_util :: sca_trace(atfs, if2_dut.clk1, "\tCLK"); sca_util :: sca_trace(atfs, if2_dut.start1, "\tSTART"); sca_util :: sca_trace(atfs, if2_dut.in, "\tINPUT"); sca_util :: sca_trace(atfs, if2_dut.out, "\tOUTPUT"); sca_util :: sca_trace(atfs, if2_dut.eoc, "\tEOC"); sc_start(400, SC_US); sca_util :: sca_close_tabular_trace_file (atfs); return 0; } -------------------

Hello All, I am modeling A2D that uses a successive approximation algorithm. I have modeled A2D converter in SystemC and SystemC-AMS. But both of the models give me some errors. SC model ends up with infinite loop, and SC-AMS model ends with segmentation fault the models are as follows: SC models: Location of the while loop could be the serious problem. I have tried changing the location in side switch statement, but error persists. //error message: stage 1: start edge stage 1: start edge stage 1: start edge stage 1: start edge stage 1: start edge stage 1: start edge stage 1: start edge ...... infinite loop // SC_A2D.h #include<systemc.h> enum adc_state {input, convert}; SC_MODULE(A2D_module) { sc_in_clk clk; sc_in_clk start; sc_in<double> ain; sc_out<sc_logic> eoc; sc_out<sc_lv<8> > dout; sc_signal <adc_state> status; void conversion_logic(); // void next_state_logic(); SC_CTOR(A2D_module) { SC_CTHREAD(conversion_logic, start.pos()); } }; //SC_A2D.cpp #include <SC_A2D.h> void A2D_module::conversion_logic() { eoc = SC_LOGIC_0; dout = "00000000"; double thresh, Vtemp; sc_lv<8> dtemp; int bit_cnt = 8; status = input; while(bit_cnt > 0) { switch (status){ cout << "begin !!!"; case input: if (start == 1) { cout << "stage 1: start edge" << endl; thresh = 5.0; Vtemp = ain; eoc = SC_LOGIC_0; status = convert; } break; case convert: if (clk == 1) { cout << "stage 2: clk edge" << endl; thresh = thresh/2.0; if (Vtemp > thresh) { cout << "stage 3: Vtemp > thresh" << endl; dtemp[bit_cnt]= '1'; Vtemp = Vtemp- thresh; } else { dtemp[bit_cnt]= '0'; } if (bit_cnt > 0) { cout << "stage 4: bit_cnt > 0" << endl; bit_cnt = bit_cnt - 1; } else { cout << "last stage: conversion" << endl; dout = dtemp; status = input; wait(10, SC_US); eoc = SC_LOGIC_1; } } break; } // end switch } // end while } // end method conversion_logic ------------------------------------------------------------------------------------------------------------- SC-AMS models: which gives segmentation fault // Error message: stage 1: Read Input stage 3: Convert Input stage 1: Read Input stage 2 : start edge stage 3: Convert Input stage 4: clk edge !!! bit_cnt = 7 stage 1: Read Input stage 3: Convert Input stage 1: Read Input stage 3: Convert Input stage 4: clk edge !!! Segmentation fault // A2D.h #include <systemc-ams> #include <systemc> #include <stdio.h> using namespace std; //ref: VHDL-AMS Model of A2D converter given in System designer's guide to VHDL-AMS on page 287 SCA_TDF_MODULE (a2d_nbit) { //port declaration sca_tdf::sca_in<double> ain; // analog input pin sca_tdf::sca_de::sca_in<bool> clk; //clock signal sca_tdf::sca_de::sca_in<bool> start; //clock signal sca_tdf::sca_de::sca_out<sc_dt::sc_logic> eoc; //end of conversion pin sca_tdf::sca_de::sca_out<sc_dt::sc_lv<8> > dout; //digitalized output a2d_nbit(sc_core::sc_module_name nm, double Vmax_ = 5.0, double delay_ = 10.0e-6, int bit_range_ = 8, bool start_x_ = 0, bool clk_x_ = 0): ain("ain"), start("start"),clk("clk"), eoc("eoc"), dout("dout"), Vmax(Vmax_), delay(delay_), bit_range(bit_range_), start_x(start_x_), clk_x(clk_x_){} void set_attributes() { set_timestep(50, sc_core::SC_US); eoc.set_delay(1); } void initialize() { eoc.initialize(sc_dt::SC_LOGIC_0); } void processing(); private: double delay; // ADC conversion time double Vmax; int bit_range; bool clk_x; bool start_x; }; // A2D.cpp void a2d_nbit :: processing() { // double Vin = ain.read(); double thresh; //Threshold to test input voltage double Vtemp; //snapshot of input voltage when conversion starts sc_dt::sc_lv<8> dtemp; //temparary output data enum state {input, convert}; int bit_cnt; state status = input; switch(status) // ref: systemC state machine example in SystemC user guide on page 171 { case input : cout << "stage 1: Read Input" << endl; if((start == true) && (start_x == false)) //if (start == true) { cout << "stage 2 : start edge" << endl; bit_cnt = bit_range; thresh = Vmax; Vtemp = ain; eoc = sc_dt::sc_logic('0'); } case convert: cout << "stage 3: Convert Input" << endl; if ((clk == true) && (clk_x == false)) //if (clk == true) { cout << "stage 4: clk edge !!!" << endl; thresh = thresh/2.0; if (Vtemp > thresh) { dtemp[bit_cnt]= '1'; Vtemp = Vtemp - thresh; } else { dtemp[bit_cnt]= '0'; } if (bit_cnt > 0) { bit_cnt = bit_cnt - 1; cout << " bit_cnt = " << bit_cnt << endl; } else { dout = dtemp; eoc = sc_dt::sc_logic('1'); status = input; } break; } default: break; } // end switch start_x = start; clk_x = clk; } ---------------------------------------------------------------------------------------------------------------- // voltage source: dummy_source.h #include<systemc-ams> #include<systemc> #include<iostream.h> #include<fstream.h> using namespace std; SCA_TDF_MODULE (dummy_src) { // sca_tdf::sca_de::sca_out<double> output; sca_tdf:: sca_out<double> output; ifstream infile; double val; dummy_src(sc_core::sc_module_name): output("output"){} void set_attributes() { set_timestep(50, sc_core::SC_US); infile.open("datalog.txt"); } void processing () { if (infile >> val) { output.write(val); } else { output.write(0.0); } } }; ------------------------------------------------------------------------------------------------------------- // top_level_entity : interface.h #include<systemc-ams> #include<systemc> #include<A2D.h> //#include<SC_A2D.h> #include<dummy_source.h> using namespace std; using namespace sc_core; SC_MODULE (interface2) { // A2D_module a2d; a2d_nbit a2d; dummy_src input_vtg; sc_core::sc_clock clk1; sc_core::sc_clock start1; SC_CTOR(interface2) :in("in"), out("out"), a2d("a2d"), input_vtg("input_vtg"), clk1("clk1", 100, sc_core::SC_US, 0.5), start1("start1", 200, sc_core::SC_US, 0.5), eoc("eoc") { input_vtg.output(in); a2d.ain(in); a2d.start(start1.signal()); a2d.clk(clk1.signal()); a2d.eoc(eoc); a2d.dout(out); } public: // sc_core::sc_signal <double> in; sca_tdf::sca_signal<double> in; sc_core::sc_signal<sc_dt::sc_lv<8> > out; sc_core::sc_signal<sc_logic> eoc; }; // top_level_entity: interface2.cpp #include<systemc-ams.h> #include<systemc.h> #include<iomanip> #include<interface2.h> int sc_main(int argc, char* argv[]) { interface2 if2_dut("if2_dut"); sca_util :: sca_trace_file* atfs = sca_util :: sca_create_tabular_trace_file("if2.dat"); sca_util :: sca_trace(atfs, if2_dut.clk1, "\tCLK"); sca_util :: sca_trace(atfs, if2_dut.start1, "\tSTART"); sca_util :: sca_trace(atfs, if2_dut.in, "\tINPUT"); sca_util :: sca_trace(atfs, if2_dut.out, "\tOUTPUT"); sca_util :: sca_trace(atfs, if2_dut.eoc, "\tEOC"); sc_start(400, SC_US); sca_util :: sca_close_tabular_trace_file (atfs); return 0; } -------------------

My typo mistake thanks Philip !!!

Hello Torsten, In the above code context, I have written following codes and encountered an error message. could you please help me to locate the mistake? Codes are as follows: -- datalog.txt -- 3.000315 3.000944 3.001572 3.002199 3.002829 3.003457 3.004085 3.004714 3.005342 3.005970 3.006599 3.007227 3.007855 3.008483 3.009112 3.009740 3.010368 3.010997 3.011625 3.012253 3.012881 3.013510 3.014138 3.014766 3.015395 ...cont... -- dummy_source.h -- #include<systemc-ams> #include<systemc> #include<iostream.h> #include<fstream.h> using namespace std; SCA_TDF_MODULE (dummy_src) { sca_tdf :: sca_out<double> output; // ifstream infile; // double val; dummy_src(sc_core::sc_module_name): output("output"){} void set_attribute() { set_timestep(25, sc_core::SC_US); } void processing () { ifstream infile; double val; infile.open("datalog.txt"); if (infile >> val) { output.write(val); } else { output.write(0.0); } } }; -- dummy_test.cpp -- #include<systemc-ams.h> #include<systemc.h> #include<dummy_source.h> using namespace std; SC_MODULE(top_level) { dummy_src vtg_src; sca_eln::sca_tdf::sca_vsource vin; top_level(sc_core::sc_module_name): vtg_src("vtg_src"), vin("vin"), n1("n1"), n2("n2"), gnd("gnd") { vtg_src.output(n1); vin.inp(n1); vin.p(n2); vin.n(gnd); } public: sca_tdf::sca_signal<double> n1; sca_eln::sca_node n2; sca_eln::sca_node_ref gnd; }; int sc_main(int argc, char* argv[]) { top_level dut("dut"); sca_util :: sca_trace_file* atfs = sca_util :: sca_create_tabular_trace_file("datalog.dat"); sca_util :: sca_trace(atfs, dut.n1, "out"); sc_core::sc_start(0.5, sc_core::SC_SEC); sca_util :: sca_close_tabular_trace_file (atfs); return 0; } -- Error Message -- Error: SystemC-AMS: Error at least one sample period must be assigned per cluster the following modules are included in the current cluster (max. 20 printed): dut.vtg_src sca_linear_solver_0 containing modules: dut.vin I tried out changing set_timestep to output.set_timestep, but the error persists !!! regards, Milind.

Hello Torsten, as per the above discussion, I have written the code for a dummy source as follows, I might need ur kind comments. (code runs with out compilation errors) #include<systemc-ams> #include<systemc> #include<iostream.h> #include<fstream.h> using namespace std; SCA_TDF_MODULE (dummy_src) { sca_tdf :: sca_out<double> output; ifstream infile; double val; dummy_src(sc_core::sc_module_name nm, sca_core::sca_time Tm_ = sca_core::sca_time(25, sc_core::SC_US)): output("output"), Tm(Tm_){} void set_attribute() { set_timestep; } void processing () { infile.open("../datalog.txt"); while (infile >> val) { output.write(val); sc_core::wait(25, sc_core::SC_US); //user guide page: 38, top block } } private: sca_core::sca_time Tm; };

Hello Torsten, thanks for the reply. The time step between the sample is constant. So I will explore the first approach. regards, Milind

Hello All, I have a problem regarding Input stimuli. I have a text file, In which I have written an AC signal. Text file example: Time output voltage (volt) 0 us 2.0 v 10 us 2.1 v 20 us 2.2 v . . . 100 us 3.0 v and so on..... I want to use this file, more specifically the "output voltage" signal as an input stimuli to a SystemC-AMS code say for example an amplifier or an A2D converter. in SystemC-AMS code, I do have a signal sca_tdf::sca_signal<double> in; how can i assign the output voltage in the text file to a "in" signal ? how can i handle time intricacies ? thanks in advance !!! regards, Milind

thanks Torsten for your detailed response. As you correctly pointed out, after removing the two initialize callbacks, the error disappeared. are there some ways to initialize the sca_tdf::sca_de::sca_in<sc_dt::sc_logic> port ? in the simulation, "eoc" and "output" remains "X" undefined. could you please tell me, if the clock connection is correct. I have declared the clock in A2D_toplevel.h, and connected directly to clk input of an a2d instance. In constructor I have defined the clock period as 10, does it take the 10 time units of "set_timestep" attribute a2d_nbit which is 1ms. regards, Milind.

Hi All, while simulating A2D convertor, I got following problems. Compilation: No Error running .exe file returns the following error message: ----------------------------------------------------------------------------------------------------------------------------------------------------------------- Warning: SystemC-AMS: Initialization for tracing of: CLK failed set wave to 0 In file: sca_trace_object_data.cpp:136 In process: method_p_0 @ 0 s Error: SystemC-AMS: Sample id (0) is greater than delay (0 while initializing port: A2D_dut.a2d.eoc In file: /home/4all/packages/systemc/2.2.0-sl4.5//include/scams/predefined_moc/tdf/sca_tdf_sc_out.h:418 In process: A2D_dut.a2d.sca_implementation_0.cluster_process_0 @ 0 s ----------------------------------------------------------------------------------------------------------------------------------------------------------------- In this regards, I have checked the complete code as well as the the files suggested in error message (/sca_tdf_sc_out.h:418), (sca_trace_object_data.cpp:136), but I did not get any clue. my codes look like this: //A2D.h SCA_TDF_MODULE (a2d_nbit) { //port declaration sca_tdf::sca_in<double> a_in; // analog input pin sca_tdf::sca_de::sca_in<sc_dt::sc_logic> start; //start signal sca_tdf::sca_de::sca_in<bool> clk; //clock signal sca_tdf::sca_de::sca_out<sc_dt::sc_logic> eoc; //end of conversion pin sca_tdf::sca_de::sca_out<sc_dt::sc_lv<8> > d_out; // digital output signal a2d_nbit(sc_core::sc_module_name nm, double Vmax_ = 5.0, double delay_ = 10.0e-3, int bit_rng = 8): a_in("a_in"), start("start"),clk("clk"), eoc("eoc"), d_out("d_out"), Vmax(Vmax_), delay(delay_), bit_range(bit_rng){} void set_attribute() { set_timestep(1, sc_core::SC_MS); eoc.set_delay(0); } void initialize() { eoc.initialize(sc_dt::SC_LOGIC_0); start.initialize(sc_dt::SC_LOGIC_0); } void processing(); private: double Vmax; // ADC maximum range double delay; // ADC conversion time int bit_range; //vector length of d_temp and d_out }; //A2D_top_level.h SC_MODULE (A2D_top_level) { a2d_nbit a2d; vtg_src input_vtg; sc_core::sc_clock clk1; void start_logic(){ while(true) { start.write(sc_dt::SC_LOGIC_0); wait(20, sc_core::SC_MS); start.write(sc_dt::SC_LOGIC_1); wait(20, sc_core::SC_MS); start.write(sc_dt::SC_LOGIC_0); sc_core::sc_stop(); } } SC_CTOR(A2D_top_level) : in("in"), out("out"), a2d("a2d"), input_vtg("input_vtg"),clk1("clk1",10, 0.5, true), start("start"), eoc("eoc") { input_vtg.out(in); a2d.a_in(in); a2d.start(start); a2d.clk(clk1.signal()); a2d.eoc(eoc); a2d.d_out(out); SC_THREAD(start_logic); } public: sca_tdf::sca_signal <double> in; sc_core::sc_signal<sc_dt::sc_lv<8> > out; sc_core::sc_signal<sc_dt::sc_logic> start; sc_core::sc_signal<sc_dt::sc_logic> eoc; }; //A2D_test.cpp int sc_main(int argc, char* argv[]) { A2D_top_level A2D_dut("A2D_dut"); sca_util :: sca_trace_file* atfs = sca_util :: sca_create_tabular_trace_file("A2D.dat"); sca_util :: sca_trace(atfs, A2D_dut.a2d.clk, "CLK"); sca_util :: sca_trace(atfs, A2D_dut.start, "START"); sca_util :: sca_trace(atfs, A2D_dut.in, "INPUT"); sca_util :: sca_trace(atfs, A2D_dut.out, "OUTPUT"); sca_util :: sca_trace(atfs, A2D_dut.eoc, "EOC"); sc_start(1.5, SC_SEC); sca_util :: sca_close_tabular_trace_file (atfs); return 0; } could you please help in solving this problem.... regards, Milind

Hello All, thanks for kind replies. The compilation errors are solved !!! The changes made in the code are highlighted in blue color..... #include<systemc-ams.h> #include<systemc> #include<A2D.h> #include<vtg_src.h> using namespace std; using namespace sc_core; SC_MODULE (A2D_top_level) { a2d_nbit a2d; vtg_src input_vtg; sc_core::sc_clock clk1; void start_logic(){ while(true) { start.write(sc_dt::SC_LOGIC_0); wait(2, sc_core::SC_MS); start.write(sc_dt::SC_LOGIC_1); wait(2, sc_core::SC_MS); start.write(sc_dt::SC_LOGIC_0); sc_core::sc_stop(); } } SC_CTOR(A2D_top_level): in("in"), out("out"), a2d("a2d"), input_vtg("input_vtg"),clk1("clk1", 100, SC_US, 0.5, true), start("start"), eoc("eoc") { input_vtg.out(in); //clk(clk1.signal()); a2d.a_in(in); a2d.start(start); a2d.clk(clk1.signal()); a2d.eoc(eoc); a2d.d_out(out); SC_THREAD(start_logic); } public: sca_tdf::sca_signal <double> in; sc_core::sc_signal<sc_dt::sc_lv<8> > out; sc_core::sc_signal<sc_dt::sc_logic> start, eoc; }; thanks ones again. regards, Milind.