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About wszhong631

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  1. hi, In uvm_phase file of uvm1.2, I understand that before_phase.m_successors.delete(after_phase) which is the 978th line code of add method should be 'before_phase.m_predecessors.delete(after_phase) ' , that is right ? 965 // IN BETWEEN 'BEFORE' and 'AFTER' PHASES 966 else if (before_phase != null && after_phase != null) begin 967 if (!after_phase.is_before(before_phase)) begin 968 `uvm_fatal("PH_ADD_PHASE",{"Phase '",before_phase.get_name(), 969 "' is not before phase '",after_phase.get_name(),"'"}) 970 end 971 // before and after? add 1 pred and 1 succ 972 begin_node.m_predecessors[after_phase] = 1; 973 end_node.m_successors[before_phase] = 1; 974 after_phase.m_successors[begin_node] = 1; 975 before_phase.m_predecessors[end_node] = 1; 976 if (after_phase.m_successors.exists(before_phase)) begin 977 after_phase.m_successors.delete(before_phase); 978 before_phase.m_successors.delete(after_phase); 979 end 980 end // if (before_phase != null && after_phase != null)
  2. thank you ,that is , when one user turn off automatic item recording , and if the user want to use register model to access some dut registers, that will be impossible.
  3. Hi, when I comile my testbench, automatic item recording has been turned off by defining UVM_DISABLE_AUTO_ITEM_RECORDING. a) set m_auto_item_recording to 0 in uvm_sequencer_base.svh, if call the function of is_auto_item_recording_enabled(),it return 0 `ifdef UVM_DISABLE_AUTO_ITEM_RECORDING local bit m_auto_item_recording = 0; `else local bit m_auto_item_recording = 1; `endif // Access to following internal methods provided via seq_item_export virtual function void disable_auto_item_recording(); m_auto_item_recording = 0; endfunction virtual function bit is_auto_item_recording_enabled(); return m_auto_item_recording; endfunction b)the follow code should be bypassed in finish_item task,if not , sequencer.end_tr(item) can triggger end_event 。 if (sequencer.is_auto_item_recording_enabled()) begin sequencer.end_tr(item); en c)In uvm_reg_map.svh, such as do_bus_write() method,after finish_item is called, the access proccess will be suspended all the way, except that end_event emitted, bus_req.set_sequencer(sequencer); rw.parent.start_item(bus_req,rw.prior); if (rw.parent != null && i == 0) rw.parent.mid_do(rw); rw.parent.finish_item(bus_req); bus_req.end_event.wait_on(); d) automatic item recording has been turned off by defining UVM_DISABLE_AUTO_ITEM_RECORDING ,The user must call the end_tr function of the uvm_driver to trigger end_event ?
  4. Problems with starting_phase

    That is "DAP" access policy,you should add "+UVM_NO_DEPRECATED" option when you compile it .
  5. hi, when the register width differs from the bus width and one register access results in a series of bus transactions,such as using 32bit-width data bus can access 64-register dut by separated two times,this can be interrupted by grabed sequence,such as interrrupt sequence, A example of transaction_order may be A_upper( upper 32 bit of A register,suppose higher priority ) -----> Interrupt service sequence(may be access interrupt clear or mask register (two times ) -----> A_Lower( lower 32 bit of A register) whether the transaction order is corrected or not ? this may cause some unright something?,thank you
  6. you must compile questasim_uvm_package.sv ,and vsim -uvmcontrol=all ,then add sequences to wave using UVM-Aware Debug windows, also,may add monitor transaction to wave using transaction record method , the version of mentor tools should 10.2b above. ,ple reference questa SIM user Mannal.
  7. Hi,I have such a question https://verificationacademy.com/forums/uvm/how-use-soft-constraint who can help me ? thanks /wszhong
  8. Hi! often,in uvm test, host controller write or read registers through addresses,so, I define some parameter in a package using `define in replace of register address. then , import the package into my test lib package, compile in order , test lib package is compiled lastly, but when compling code ,report macro address can't find? How to using package rightly in UVM? Large projects may have many packages with complex interdependencies,How to using it rightly ? thanks. /wszhong
  9. Hi! uvm_component_name_check_visitor This specialized visitor analyze the naming of the current component. The established rule set ensures that a component.get_full_name() is parsable, unique, printable to order to avoid any ambiguities when messages are being emitted. ruleset a legal name is composed of allowed charset “A-z:_0-9[](){}-: “ whitespace-as-is, no-balancing delimiter semantic, no escape sequences path delimiter not allowed anywhere in the name whether the name abc:_[] is legal or not ?how to use it?
  10. hi, I will be ready to build one layer protocol testbench, top level sequence item is transmit to lower level sequencer with large payload of data packet. assuption that 1) trans_item is toper level sequence item(transaction layer item); 2) link_item is lower level sequence item(ie,link layer item); patial code as follows: class trans_item extends uvm_sequence_item; rand bit [31:0] mess_data[]; rand bit [15:0] mess_len; constraint C_mess{ soft mess_data.size()==mess_len; solve mess_len before mess_data; } ................ class link_item extends uvm_sequence_item; rand bit [31:0] mess_data[]; rand bit [15:0] mess_len; constraint C_mess{ soft mess_data.size()==mess_len; solve mess_len before mess_data; } ................ class top_sequence extends uvm_sequence #(trans_item); rand bit [31:0] trans_data[]; rand bit [15:0] trans_len ; constraint C_len{ trans_len==40; trans_data.size()==trans_len; solve trans_len before trans_data; } .... virtual task body() `uvm_do_with(req,{req.mess_len==local::trans_len; ........................ foreach(local::trans_data) req.mess_data==local::trans_data;}) req.print(); endtask endclass class trans_to_link_seq extends uvm_sequence #(link_item); uvm_sequencer trans_sequencer; trans_item trans_req; link_item link_req; ...... virtual task body(); trans_sequencer.get_next_item(trans_req); trans_req.print() // why can't print mess_data ........ `uvm_do_with(link_req,{link_req.mess_len==trans_req.mess_len; .................. foreach(trans_req.mess_data) link_req.mess_data==trans_req.mess_len;}) ............. endclass next, supposing that trans_sequencer has connected to link_sequencer by uvm_seq_item_pull_port ,seq_item_export then , In test start top_sequence and trans_to_link_seq in fork jion statement; class trans_test extends uvm_test; virtual task main_phase (uvm_phase phase); phase.raise_objection(this,""); fork top_sequence.start(env.agent.trans_sequencer); trans_to_link_seq.start(env.agent.link_sequencer); join_any During the simulation,printing mess_len is not 40, questasim10.2c simulator has not reported assertion failed,in practual constraint is failed, why can't print mess_data? how dynamic array and x_len is constrainted? how to send large payload of data packet to lower sequence or lower driver?
  11. sorry,payloadseqment is a mis-spelling error when written this question. in sequence_item.svh, rand [7:0] payloadsegment[]; // payloadsegment that payload of some packets https://verificationacademy.com/forums/uvm/why-payloadsegment0-not-legal-c-identifier-namebut-payloadseqment0 Dave_59 says as follows "This warning is generated by Questa's built-in UVM-aware debug facilities. In order to use the debugging tools, the UVM created paths need the ability to be parsed by the command line. All vendor tools have this problem. You can ignore these warnings if you do not plan to use these debug facilities. Note that the upcoming UVM 1.2 standard plans to require proper identifier names, not just any string. You will get an error if you do not fix them. See http://www.eda.org/svdb/view.php?id=4712 " indeed, if not add "+incdir+$(questa_uvm_pkg) $(questa_uvm_pkg)/questa_uvm_pkg.sv", lot of warnings that sees if very Annoying will not be reported。
  12. in order to watch UVM_details windows in questasim10.2c/10.2b,vlog option + questa_uvm_pkg options. Makefile as follows: questa_uvm_pkg=/app/mentor/questasim_10.2c/questasim/verilog_src/ vlog +incdir+$(uvm_home)/src $(uvm_home)/src/uvm.sv \ +incdir+$(questa_uvm_pkg) $(questa_uvm_pkg)/questa_uvm_pkg.sv ............... under of simulation,report warning as follows: questasim/verilog_src/questa_uvm_pkg_1.2/src/questa_recorder.svh(364) @4080840000: reporter [iLLEGALNAME] 'payloadsegment[0]' is not a legal c identifier name.change to questasim/verilog_src/questa_uvm_pkg_1.2/src/questa_recorder.svh(366) @4080840000: reporter [iLLEGALNAME] 'payloadsegment_0_' Attibutes mus be named as a legal cidentifier. and in monitor.svh, foreach(payloadsegment) payloadsegment=data; and in UVM_details window, as sequence is added to waves ,we sees randomized sequence item ,payloadsegment_0_,payloadsegment_1_,payloadsegment_2_。 why payloadsegment is not legal c identifier?! but if the same codes rerun in questasim10.1d,above warning not reported.