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  1. Synopsys's Mehta recognized for his significant role in Accellera's growth worldwide Elk Grove, Calif., May 31, 2016 -- Accellera Systems Initiative (Accellera), the electronics industry organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards, announced today that Shrenik Mehta is the recipient of the fifth annual Accellera Leadership Award. The award recognizes Shrenik's vision, leadership and contribution to standards development, governance and promotional activities on behalf of the organization. The award will be presented at the Design Automation Conference (DAC) during the Accellera breakfast and town hall meeting on Tuesday, June 7. Read the full press release...
  2. The standard will be available as part of the Accellera-sponsored IEEE Get Program Elk Grove, Calif., May 3, 2016 — Accellera Systems Initiative (Accellera), the electronics industry organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards, announced today that SystemC AMS (Analog/Mixed Signal) has been released by the IEEE Standards Association (IEEE-SA) as IEEE 1666.1™-2016. It is available for download at no charge under the Accellera-sponsored IEEE Get Program. Read the full press release...
  3. IEEE P1800.2™ working group issues Call for Participation Elk Grove, Calif., July 30, 2015 – IEEE Standards Association (IEEE-SA) and Accellera Systems Initiative (Accellera), the electronics industry organization focused on electronic design automation (EDA) and intellectual property (IP) standards, announced today that the Accellera Universal Verification Methodology (UVM) 1.2 will be submitted as a contribution to the IEEE P1800.2™ working group for further standardization and maintenance once the working group has been established at its first meeting on August 6, 2015. A Call for Participation has been distributed for the first meeting. View the full press release ...
  4. What if I were to tell you that I attended a conference where people were really excited to be there, where the exhibit hall was filled with a crush of people making their way from booth to booth, talking with exhibitors and exchanging business cards madly. A conference where the South of the exhibit hall was dominated by Synopsys, the East by Cadence, and the West by Mentor, and where at the happiest hour, libations and snacks flowed freely in a sub-set of the booths and the whole exhibit hall ... ... View the full article ...
  5. San Jose, Calif., March 2, 2015 - Accellera Systems Initiative (Accellera), the electronics industry organization focused on electronic design automation (EDA) and intellectual property (IP) standards, announced today that the Accellera Universal Verification Methodology (UVM) 1.2 standard is proceeding to IEEE standardization. Already proven in the electronics industry, the UVM standard will benefit from worldwide recognition and formalization, and will undergo the first step toward being ... ... View the full article ... View supporting industry quotes ...
  6. Elk Grove, Calif., February 25, 2015 -- Accellera Systems Initiative (Accellera) announced today that Justin Refice, a member of the Universal Verification Methodology Working Group (UVM WG), is the recipient of the fourth annual Accellera Technical Excellence Award. The award is being presented at the Design and Verification Conference and Exhibition (DVCon) on Monday, March 2, 2015 during the Accellera Day luncheon from 12:00-1:30pm at the DoubleTree Hotel in San Jose, California. The award ... ... View the full article ...
  7. View supporting quotes from Agnisys, Cadence, Mentor Graphics, Sonics, Synopsys, and more. View the full article ...
  8. Elk Grove, Calif., USA, February 11, 2015 - Accellera Systems Initiative (Accellera), the electronics industry organization focused on electronic design automation (EDA) and intellectual property (IP) standards, announced it has established a new working group with the charter to develop the electronic industry's first standard for portable test and stimulus. When completed and adopted, this standard will enable a single specification that will be portable from IP to full system and ... ... View the full article ...
  9. Proposed standard to specify verification intent and behaviors reusable across multiple target platforms - Published by Electronic Engineering Journa ... View the full article ...
  10. Accellera created a working group for the portable test and stimulus, which would allow engineering teams to create the test once and be able to run it throughout the flow. - Published by Semiconductor Engineerin ... View the full article ...
  11. Last week I had a chance to chat by phone with Accellera Chair Shishpal Rawat, and when I say chance that's accurate. Rawat is so busy these days, it's hard to believe he has time for any extraneous conversations. Not only does he have a full-time job at Intel, he has been chair of Accellera for four years and now is ramping up to take over the reins at CEDA at well. - Published by EDACaf ... View the full article ...
  12. New verification standard readied for submission to IEEE; 90-day public comment period begins. - Published by Semiconductor Engineerin ... View the full article ...
  13. Napa, Calif., USA, 24 June 2014 - Accellera Systems Initiative (Accellera), the electronics industry organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards, announced it released a new version of its Universal Verification Methodology (UVM) class reference document, UVM 1.2 for SoC (system on chip) verification. UVM 1.2 improves interoperability and reduces the cost of IP development and reuse for each new project. The ... ... View the full article ...
  14. San Francisco, Calif., June 3, 2014 (at the Design Automation Conference) -- Accellera Systems Initiative (Accellera), an independent non-profit organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards, announces it has developed new verification and design modeling extensions for its Verilog-AMS standard. Verilog-AMS provides powerful structural and behavioral modeling capabilities for mixed-signal designs in which the ... ... View the full article ...
  15. Napa, Calif., USA, 28 May 2014 - Accellera Systems Initiative, the electronics industry organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards, has named Accellera board member Yatin Trivedi as the recipient of its 2014 Leadership Award. The Award recognizes the vision, leadership and contribution to standards development, governance and promotional activities of the organization. The Award will be presented at the Design ... ... View the full article ...
  16. Napa, Calif., April 22, 2014 - Accellera Systems Initiative announces two new libraries have been released for the SystemC core language (SystemC 2.3.1) and SystemC verification (SCV 2.0). Ratified as IEEE Std. 1666-2011 "Standard SystemC Language Reference Manual, "SystemC is a high-level language used in the design and development of electronic and embedded systems. The SystemC 2.3.1 proof of concept library is an update to the standard that was released in 2011 which ... ... View the full article: http://www.accellera.org/news/pr/view?item_key=a09d504af4e6c3b4b3f853ad2860cc911e205d4b
  17. Evgeny, Your account was stuck in "validating" mode, and you must be logged in with an active member account in order to download files. I've validated your account, so you should no longer see this error. Best regards, Admin
  18. San Jose, Calif., March 3, 2014 (at the Design and Verification Conference and Exhibition) -- Accellera Systems Initiative (Accellera) announces today that Andrew (Andy) Goodrich, a member of the SystemC Language Working Group (LWG), is the recipient of the third annual Accellera Technical Excellence Award. The award is being presented at the Design and Verification Conference and Exhibition (DVCon) on Accellera Systems Initiative Day, March 3, 2014 at the ... ... View the full article ...
  19. Napa, California, USA - February 13, 2014 - Accellera Systems Initiative (Accellera), the not-for profit organization dedicated to create, support, promote, and advance system-level design, modeling, and verification standards for use by the worldwide electronics industry, will host its annual Accellera Day on Monday, March 3. The day-long event kicks off the 2014 DVCon (Design and Verification Conference and Exhibition) and features in-depth tutorials from experts and users on the latest in electronic design and intellectual property standards. Accellera Day is Monday, March 3, 8:30am-4:30pm, and kicks off DVCon 2014, to be held through March 6 at the DoubleTree Hotel in San Jose, Calif. A booth crawl in the Expo will be held from 5:00pm-7:00pm. View full article > http://www.accellera.org/news/pr/view?item_key=d011f4289a57d315d49b35e0e1f8d0fc4fde2c2f
  20. Accellera Day at DVCon Monday, March 3, 2014 8:30am - 7:00pm DoubleTree Hotel, San Jose CA Accellera invites you to a special day dedicated to technical standards at the 2014 Design and Verification Conference. Connect with experts and users as we learn, share, and network on the latest in EDA and IP standards innovations. Tutorial: UVM™ - What’s Now and What’s Next Tutorial: Using UPF for Low Power Design and Verification Lunch Panel and Technical Excellence Award Presentation Tutorial: Case Studies in SystemC™ Tutorial: Experience the Next ~Wave~ of Analog and Digital Signal Processing Using SystemC™ AMS 2.0 Tutorial: OCP: The Journey Continues DVCon Expo - Booth Crawl View full details >
  21. Napa, Calif., USA, 15 October 2013 - Accellera Systems Initiative (Accellera), an independent non-profit organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards, announces it has acquired assets of the Open Core Protocol International Partnership (OCP-IP). This asset transfer includes the current OCP 3.0 standard and supporting infrastructure, which facilitates reuse of IP blocks used in the design of semiconductor ... ... View the full article ...
  22. GRENOBLE, France, March 19, 2013 (at the Design Automation and Test in Europe Conference) - Accellera Systems Initiative, an independent non-profit organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards for design and verification, today announces completion of the SystemC® Analog /Mixed-Signal(AMS) 2.0 extensions. SystemC AMS 2.0 is an industry-driven mixed-signal standard for electronic system-level design. The SystemC AMS 2.0 language reference manual (LRM) is available for download ... View the full article: http://www.accellera.org/news/pr/view?item_key=88aa269bcefcfb819e6daf9d73cdca118d3fce5a
  23. San Jose, Calif., USA, 25 February 2013 (at the 2013 Design and Verification Conference) -- Accellera Systems Initiative (Accellera) announce today they have once again partnered with the IEEE Standards Association (IEEE-SA), a globally recognized standards-setting body within the IEEE, to deliver a leading electronic design and verification standard to engineers and chip designers worldwide. The revised version of the IEEE 1800 "Standard ... ... View the full article: http://www.accellera.org/news/pr/view?item_key=fb54cca2b7ac0cdcfd6ffacb85692f1a808adab0
  24. Do design and verification engineers care about EDA standards? If the Accellera Systems Initiative "Town Hall" meeting at DVCon 2013 Feb. 25 is any indication, the answer is an emphatic yes. A packed audience attended a lively, hour-long meeting in which non-stop questions were answered by Accellera and IEEE standards developers. - Published by Cadence Industry Insights Blo ... View the full article ...
  25. San Jose, California, USA, DVCon-21 February 2013-Accellera Systems Initiative (Accellera) announced today that Janick Bergeron, a member of the Verification Intellectual Property (VIP) Technical Subcommittee (TSC), is the recipient of the second annual Accellera Technical Excellence Award. The award is being presented at the Design & Verification Conference (DVCon) on Accellera Systems Initiative Day, February 25, 2013 at the DoubleTree Hotel in San ... ... View the full article: http://www.accellera.org/news/pr/view?item_key=0187f877445369468801500478e7a4e264ddad0e