Those questions are covered in detail in paragraphs 14.1 and 14.2 of SystemC standard. Can't answer in a better way.
TLM2.0 simulations are not cycle-accurate, so you don't have clock edge events. In AT modeling style you should call wait(delay) after each transport call. In LT modeling style all initiators are temporaly decoupled and can run ahead of simulation time, usually for a globally specified time quantum.
For debugging you can use the same techinques as in cycle-accurate modeling:
Source-level debugging with breakpoints and stepping
Transaction and signal tracing
Comparing with RTL, debugging using waveform won't be that effective, because in AT/LT modeling state of model can change significantly in a single simulator/waveform step. Usually preffered way is combination of logging and source-level debug. Debugging TLM models is harder comparing to RTL. Also C++ is much more complex and error-prone comparing to VHDL/Verilog.