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  1. 9 points
    Admin

    Welcome!

    Welcome to the Accellera Systems Initiative forums. Please register to start new topics or reply to existing topics. We have resently migrated our UVM forums from UVMWorld to this site. If you were registered on the previous UVM forum site, you should be able to log into the forums using your username and password from the UVMWorld forums. If you had an account on both the UVMWorld forums and the Accellera forums and these accounts used the same email address, then log in with the username and password of the forums.accellera.org account, not your UVMWorld account. If you do not remember your password, you may reset it. If you have any questions about using the forums, click the Help button at the bottom of any forum page. If you need any help with your account and you are logged into the site, click the Messenger icon (a letter) in the upper right of your screen, click Compose New, enter “admin” in the Recipient’s Name field, compose your message, and then click Send. You may also send an email to admin@lists.accellera.org. Thank you, Accellera Systems Initiative
  2. 7 points
    India SystemC User Group Conference (ISCUG) A platform to discuss the SystemC based next generation methodologies for design and verification of Electronics Systems (Semiconductor Chips + Embedded Software) Tutorial Day: April 14, 2013 (Sunday) Conference Day: April 15, 2013 (Monday) Venue: Noida, India Register for the event at www.iscug.in. Early bird discount ends on February 28th, 2013. To receive regular updates about the event, register your email at www.iscug.in and follow www.facebook.com/iscug. For sponsorship opportunities, contact info@iscug.in About ISCUG The India SystemC User's Group (ISCUG) organization aims to accelerate the adoption of SystemC as the open source standard for ESL design. ISCUG provide a platform to share the knowledge, experiences and best practices about SystemC usage. ISCUG organize an annual conference which provides a platform for the SystemC beginners, the SystemC experts, ESL managers and the ESL vendors to share their knowledge, experiences & best practices about SystemC usage. The event will also be useful for: SoC Architects involved in architectural exploration, performance optimization, power optimization etc.. Embedded software engineers who want to explore usage of Virtual Platforms for embedded software development Chip verification engineers who want to explore SystemC based verification methodologies Chip design engineers who want to explore SystemC as the language for chip design at higher abstraction level The event is designed on the pattern of similar events happening worldwide: NASCUG, ESCUG, Japan SystemC Forum, etc. Participate You may participate in ISCUG as a speaker. Submit your abstract at www.iscug.in before February 15, 2013. The abstract will be reviewed by the technical review committee; the committee reserves the right to make final decision on speaker selection. You may present a topic related to SystemC modelling, covering virtual platforms, transaction-level modeling, high-level synthesis, SystemC-AMS, modeling for performance analysis, modellng for architectural exploration, SystemC-based SoC verification methodology, or any other topic related to SystemC modeling. You may also present a success story of SystemC adoption in your company. Tutorial Day: There will be a full day of tutorials running in parallel. To participate as a speaker, send details to info@iscug.in. First Half (Before Noon): SystemC and TLM 2.0 Introductory Tutorial Second Half (After Noon): Two/three tracks in parallel (details yet to be finalized) Advanced modeling techniques Virtual platforms for embedded software development and pre-silicon HW/SW co-verification High-level synthesis using SystemC SystemC-based verification methodologies Contact Web: www.iscug.in Email: info@iscug.in
  3. 6 points
    GRENOBLE, France, March 19, 2013 (at the Design Automation and Test in Europe Conference) - Accellera Systems Initiative, an independent non-profit organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards for design and verification, today announces completion of the SystemC® Analog /Mixed-Signal(AMS) 2.0 extensions. SystemC AMS 2.0 is an industry-driven mixed-signal standard for electronic system-level design. The SystemC AMS 2.0 language reference manual (LRM) is available for download ... View the full article: http://www.accellera.org/news/pr/view?item_key=88aa269bcefcfb819e6daf9d73cdca118d3fce5a
  4. 6 points
    Napa, California, USA - February 14, 2012 - Accellera Systems Initiative, the not-for profit organization dedicated to create, support, promote, and advance system-level design, modeling, and verification standards for use by the worldwide electronics industry, will host its annual Accellera Systems Initiative Day on Monday, February 25. The day-long event kicks off the View the full article: http://www.accellera.org/news/pr/view?item_key=07fecbd19a605a7a27dbe42d8e86fe2ae56f46e8
  5. 6 points
    David Black

    Deleting dynamic objects

    You are correct that SystemC does not automatically delete objects. The reason many coders ignore destructors for SystemC modules/objects is several fold: sc_object's (which includes sc_module's, sc_port's, sc_signal's, sc_prim_channel's, etc...) are created during elaboration and would not need to be destructed until the end of simulation when typically a SystemC program simply exits. Thus the operating system will mop up for you. For example: int sc_main(int argc, char* argv[]) { top_module top_instance("top_instance); //< Construct the design hierarchy aka elaborate sc_start(); //< run the simulation return 0; //< exit the simulator and allow OS to clean up } SystemC coders are somewhat lazy and given the above example rationalize it away This is how they were taught (sad but true) That stated, it is probably worth noting that this situation may not always be the case, and some SystemC coders do write destructors (e.g. myself). It should be noted that in a co-simulation environment, the assumption of exiting after simulation may not be true. A vendor simulator might even presume to restart a simulation. Thus I argue it is better to create destructors as good C++ programming habit. TIP: Use the C++11 std::unique_ptr<T> instead of raw pointers. Assumes you can use this class. For older versions of C++, you might consider std::auto_ptr<T>, which is deprecated as I understand it.
  6. 5 points
    Do design and verification engineers care about EDA standards? If the Accellera Systems Initiative "Town Hall" meeting at DVCon 2013 Feb. 25 is any indication, the answer is an emphatic yes. A packed audience attended a lively, hour-long meeting in which non-stop questions were answered by Accellera and IEEE standards developers. - Published by Cadence Industry Insights Blo ... View the full article ...
  7. 5 points
    apfitch

    b-transport interface

    Hi Reza, The idea of the quantum is that a process does *not* give up to the scheduler until it decides enough local time has passed. For instance, imagine the current time (as returned by sc_time_stamp()) is 1000ns. My initiator has a local sc_time variable t. I initialise t to e.g. 10 ns. An initiator thread executes b_transport(tx, t); That means my local time is now 1010ns (but sc_time_stamp() has not changed, and no other process has run). The target which implements b_transport, now updates t by 100ns i.e. t now contains 110ns. In other words, the target is "pretending" it took 100ns to process my request, and my local "pretend" time is 1110ns. I can then call b_transport again with t = 110 + 10 = 120 ns; The target returns with 220 ns; and so on. So in answer to one of your questions, yes there can be many calls to b_transport within a quantum. Let's now suppose the global quantum is set to 500 ns. Eventually, my local time offset is greater than 500 ns. At that point my initiator calls wait(), and another initiator can run. SystemC time is still at 1000 ns, sc_time_stamp() hasn't changed. The second initiator runs sending calls back and forth until its local time offset exceeds the global quantum. It then calls wait(). Eventually all initiators have run and suspended. sc_time_stamp() increases, and off we go again. Now to keep track of that yourself would be possible, but boring to write the code - so in tlm_utils there is a utility called the tlm_quantum_keeper. The idea is that each initiator has its own tlm_quantum_keeper instance, and that's what keeps track of the local time offset. So the answer to "who manages the time" is either "you do - good luck!". Or use tlm_utils::tlm_quantum_keeper (much easier). In your third example, the idea of the delay parameter is that this represents the offset from systemc time (sc_time_stamp()). In my description above, I assumed the target did *not* call wait. However if the target *does* call wait, then the offset must be reset to 0 ns, because sc_time_stamp() has increased. I hope this helps, regards Alan P.S. I suppose I should really try and sell you a training course http://www.doulos.com/content/training/systemc_tlm2.php
  8. 4 points
    San Jose, California, USA, DVCon-21 February 2013-Accellera Systems Initiative (Accellera) announced today that Janick Bergeron, a member of the Verification Intellectual Property (VIP) Technical Subcommittee (TSC), is the recipient of the second annual Accellera Technical Excellence Award. The award is being presented at the Design & Verification Conference (DVCon) on Accellera Systems Initiative Day, February 25, 2013 at the DoubleTree Hotel in San ... ... View the full article: http://www.accellera.org/news/pr/view?item_key=0187f877445369468801500478e7a4e264ddad0e
  9. 4 points
    "Accellera Systems Initiative has released the version 2.3.0 of its SystemC open source proof-of-concept library. The offering comes free of charge to the global electronic design community, the organization noted. ... View the full article ...
  10. 4 points
    "This week, Accellera Systems Initiative is announcing a new version of its SystemC library, Version 2.3 to be exact. There hasn't been a new version since way back in 2005 with Version 2.1 (albeit 2.2, a bug-fix release, was published in 2006), so this is the culmination of a lot of hard work." - Published by EDACaf ... View the full article ...
  11. 3 points
    ytakatsukasa

    Could anybody help me with QEMU ??

    Hi Mohit QEMU is an open source software mostly written in C. It emulates different architectures (ARM,MIPS, PPC, and more) from host and can run binaries on it. So you can boot android for arm on x86 PC. As far as I know the typical use cases of QEMU are System Emulator Frontend for Virtualization As a system emulator, android sdk uses QEMU to boot android to let developer check the application on x86 pc not on arm development board. Xilinx Xynq development kit also uses QEMU to run the software for the FPGA on x86 pc. For virtualization, QEMU is used to virtualize x86 pc on x86 pc (or arm on arm) with KVM or XEN. Shorter answer: Yes, Green Socs and TLMu are famous project for it. Iguess there may be similar projects more. Longer answer: QEMU consists of many kinds of processor models and peripheral models, so many tried to use it with SystemC. I also succeeded to boot arm linux on my customized TLMu( QEMU processor model + SystemC peripheral models). IMHO QEMU has 3 difficulties for integrating with SystemC. Building QEMU is sometimes troublesome because of its dependencies on many libraries. QEMU is written in C with gtk-like object system and with so many global/static variables. It is tough to understand and modify the source code. Global variables prevent you from multi-instantiation. QEMU source code is always changing and its speed is fast. It will be a painful work to catch up with the mainline release after you fork QEMU. QEMU is a really really useful software, actually I use it for virtualization and appreciate it. But honestly its source code is not something that I would love to recommend for learning material. I hope you will find a cool way to integrate it with SystemC. Regards, Yutetsu.
  12. 3 points
    Philipp A Hartmann

    problem with constructor

    As the error says (emphasis mine) you need a default constructor (a constructor without arguments) in your case. In the module, you create an instance of 'decimal' without explicitly initializing it in the constructor of 'seprate_digit'. Theoretically, you could use an initializer list: SC_CTOR (seprate_digit) : in("in"), clk("clk"), d("d") // port names -> recommended practice , decimal(0,0,0,0) // <-- explicitly initialize decimal member Since you use 'decimal' as a signal type, you'll definitely need a default constructor. This could look like the following decimal() /* : dec0(), dec1(), dec2(), dec3() */ // optional, as sc_int has an explicit default constructor {} Secondly, you'll need to define more helper functions to use sc_signal with your own data types, see http://www.doulos.com/knowhow/systemc/faq/#q1 Greetings from Oldenburg, Philipp NB: Why do you post the question three times in 10 minutes? ;-)
  13. 3 points
    apfitch

    systemC synthesis guidlines

    Hi Mohit, 1. The important issue is not the language, but the technology. Behavioural synthesis tools generally deduce a combination of state machines (for control) and datapath (for signal processing). The key thing is that you as a designer do not have to write the micro-architecture yourself. Hence behavioural synthesis is potentially more productive than standard RTL synthesis. That argument is language independent. A behavioural VHDL tool would be more productive than an RTL VHDL tool. Writing RTL in SystemC would be no more productive than writing RTL in VHDL or Verilog. So your question "why do we require SystemC sythesis when we have HDL synthesis" would be better as "why do we need behavioural synthesis rather than RTL synthesis". And the answer is you only need it if it's better for you in some way (faster time-to-market for instance). No-one is forcing you to use behavioural synthesis :-) 2. I don't know if SystemC synthesis tools are interoperable. 3. How come tools exist even though the synthesis standard is a draft? EDA vendors are free to ignore standards :-) Standards only get adopted (and developed) if EDA vendors and users can see value in those standards. So I guess no-one is motivated to finish the synthesis standard. The key thing about the synthesis standard (as opposed to a language standard) is it's trying to guide how a tool may interpret SystemC code. EDA vendors see that as a legitimate area of product differentiation. The same thing happened with VHDL 1076.6 - the vendors essentially ignored it. 4. You may mix synthesisable and non-synthesisable code, you just have to hide the code using the pre-processor or meta-comments. The same is true in VHDL and Verilog - you can include non-syntheisable code, but it is typically hidden using meta-comments, e.g. -- synthesis translate_off code that won't synthesize goes here -- synthesis translate_on regards Alan
  14. 3 points
    apfitch

    Why SystemC and who uses it ???

    Hi Karandeep, the main usage of SystemC is in design of large SoC. As such, it is mainly used by large semiconductor companies. Typically such a company may be developing a large chip (very large!). That causes a number of problems How to concurrently develop software and hardware? How to start writing software drivers before the RTL design is finished? How to develop a reference model to be used in with Testbench Automation/Constrained Random Verification environments? How to build and re-use IP models for use in a high level model? (otherwise every company has to build processor models, bus fabric models etc from scratch). If developing a completely new chip, how to analyse bus bandwidths, data flows and so on - especially with multiple processors competing for bus resource. SystemC allows a company to attack all these problems - by building a model with accurate register modelling, the model may be used for software device driver development. Typically using very fast processor models and loosely timed styles, that model can boot multiple pieces of software on processor models at high speed. With some refinement, a similar model can be used as a reference for TBA/CRV. You need a reference model, so why not re-use it? For architectural analysis an approximately timed model is better suited - but remember you might not need it if you are refining an existing platform rather than starting from scratch. For re-usable models - that's the point of TLM2, to create a standard API to allow exchange of models. Existing APIs (SCML, TAC etc) can gradually migrate to a standard, promoting re-use. Finally why SystemC? Why not use SystemVerilog; or Java; or Python; or Haskell; or <fill in your favourite language here>? There are many factors, some practical, some political, some historical. In my opinion the main factors are/were 1. System Architects speak C++ / Excel / Word /Matlab. They don't speak Verilog/SystemVerilog/VHDL 2. SystemC started in 1999 3. EDA vendors got behind SystemC and developed tools to allow virtual platforms to be built I hope that helps, regards Alan P.S. Regarding finding references / information/ facts, the key point to remember is that the world of SoC/VLSI design is small. There just aren't many companies with the resources to develop large chips; and within those companies, there just aren't many system architects / modellers. In a typical large chip development they'll probably be many software engineers - probably considerably more than hardware engineers; within hardware, they'll be a few back-end people; a reasonable number of RTL designers; a similar or larger number of verification engineers; and perhaps 1 system architect. So SystemC just isn't used by large numbers of people, compared the Verilog/VHDL/SystemVerilog.
  15. 3 points
    Hello all, Accellera Systems Initiative annouced the release of the SystemC AMS 2.0 standard. The AMS 2.0 standard is available as Language Reference Manual and can be downloaded here: http://www.accellera.org/downloads/standards/systemc Note that this standards update does not contain the user's guide. The AMS working group is working hard to release this document in the future. Now that AMS 2.0 is available, we anticipate that EDA companies and/or research institutes are getting inspired to make a proof-of-concept compatible with this standard. This means that today there is no simulation platform available, but we expect in the future it will become available. Also ask your preferred EDA vendor or partner when SystemC AMS 2.0 gets integrated in the tool and flow. Feel free to post your questions or remarks on the new SystemC AMS 2.0 standard in this forum. Regards, Martin Barnasconi AMS working group chair
  16. 3 points
    David Black

    SystemC in Visual Studio 2012

    Try: 1. Installed Visual C++ 2012 Express Edition (Note - won't work on XP only Windows 7/8) 2. Download Systemc-2.3.0.tgz 3. uncompress systemc-2.3.0.tgz 4. Assuming in c:\systemc-2.3.0 5. copy msvc80 to msvc11 (optional, but helps if you attempt to run regressions) 6. Run Visual C++ 2012 EE and open msvc11\systemc\systemc.sln 7. Upgrade is offered - click OK 8. Menu Build > Build Solution Build failed due to warning 4005 Edit sc_cmnhdr.h line 75 and add a test for _MSC_VER == 1200 as follows: // MSVC6.0 for() scope bug #if defined(_MSC_VER) && (_MSC_VER == 1200) #define for if( false ); else for #endif Now it should build. 9. Add an environment variable SYSTEMC set to c:\systemc-2.3.0\ 10. Set library, src, include paths as for Visual C++ 2010 Note: to find the property pages, load in a project (e.g. ex6 from the course). Then do View > Other Windows > Property Manager Expand the project name until you find Debug | Win32 > Microsoft.CPP.Win32.user and set the include and library directories to $(SYSTEMC)\src $(SYSTEMC)\msvc11\systemc\debug
  17. 3 points
    San Jose, Calif., USA, 25 February 2013 (at the 2013 Design and Verification Conference) -- Accellera Systems Initiative (Accellera) announce today they have once again partnered with the IEEE Standards Association (IEEE-SA), a globally recognized standards-setting body within the IEEE, to deliver a leading electronic design and verification standard to engineers and chip designers worldwide. The revised version of the IEEE 1800 "Standard ... ... View the full article: http://www.accellera.org/news/pr/view?item_key=fb54cca2b7ac0cdcfd6ffacb85692f1a808adab0
  18. 3 points
    apfitch

    SystemC Guides for Beginners

    On our website there's a tutorial and a number of videos and examples of TLM2 and SystemC (see www.doulos.com/knowhow/systemc and www.doulos.com/knowhow/systemc/tlm2), though I must admit the tutorial is quite hardware orientated. There used to be a tutorial on the Forte Design Systems website, but I can't find it any more. I would recommend downloading the latest standard (IEEE 1666-2011) via http://www.accellera.org/downloads/ieee/ I certainly would *not* recommend either the 2.0 user guide or the 2.0.1 reference manual, they are very out-of-date. To paraphrase someone, every time I see sc_bit I reach for my revolver :-) Probably the best general book is "SystemC from the Ground Up" by David C Black, Jack Donovan, Bill Bunton and Anna Keist. regards Alan
  19. 3 points
    The old syntax sc_start(int) was deprecated when we removed the sc_set_default_time_unit(sc_time) concept. Your choices for sc_start are limited to sc_start(void), sc_start(sc_time) and sc_start(double),sc_time_unit).
  20. 3 points
    Following are European SystemC Users' Group events at the DATE Conference 2013 in Grenoble, France. 27th European SystemC Users' Group Meeting Tuesday March 19th, 2013 6:30pm - 9:30pm Room TBA Join the Accellera update and town hall meeting around Accellera technologies and standards. We give insights into their influence and requirements for future design strategies. More information, including registration and the final program, will be available at: http://www.ti.uni-tu...10.0.html?&L=0/. European SystemC Users' Group Workshop ESL -- Putting the Pieces Together: Integrating SystemC Design and Verification with AMS and Algorithm Design Friday March 22nd, 2013 8:30am - 4:50pm Room TBA This full-day workshop is focused on the integration of SystemC design and verification with AMS and algorithm design. It gives deep insights on how techniques may collaborate and converge. These topics are gaining more and more interest because a seamless integration of all relevant design and verification techniques is crucial. Besides digital hardware design, this is substantially important for the areas of algorithm and AMS design. The keynote from STMicroelectronics discusses the challenges of design flow integration in multi physical domain applications. The workshop includes four invited sessions from TU Kaiserslautern, NXP, Fraunhofer IIS, and Bosch -- providing knowledge about the core technologies, their application, and integration into ESL design flows. The core session’s part is complemented by an interactive discussion with the audience. This session is organized in town hall meeting style. This event requires registration. For an agenda and to register, see http://www.date-conf...nce/workshop-w1.
  21. 3 points
    NAPA, Calif. - November 15, 2012 - Nominations are being accepted now through Friday, January 18 for the 2013 Technical Excellence Award sponsored by Accellera Systems Initiative (Accellera). The Award recognizes outstanding contributions in the creation of electronic design automation (EDA) and intellectual property (IP) standards by a member of an Accellera technical committee. Standards created by Accellera are contributed to the IEEE Standards Association ... ... View the full article ...
  22. 3 points
    Hi Sumit, header guards won't necessarily help. They stop two header files being included sequentially - but if you have a function *body* in the header, and include that header in two independent files, you'll still get multiple definitions at link time. My guess is that Timmy is #including a gnoise.cpp. In that case the fix is to make a gnoise.h with the function prototype, with your header guards of course, and include the .h not the .cpp, regards Alan
  23. 3 points
    Napa, Calif., USA, 16 July 2012 - Accellera Systems Initiative announces the release of version 2.3.0 of its SystemC open source proof-of-concept library, now available at no charge to the worldwide electronic design community. Compatible with the newly revised IEEE 1666 "Standard SystemC Language Reference Manual," announced by the IEEE Standards Association in November 2011, version 2.3.0 provides a number of important new features, ... ... View the full article ...
  24. 2 points
    Hello Geniuses, in my ADC design, I have a output signal "eoc" (end of conversion), I declared it in port declaration like below sca_tdf::sca_de::sca_out<sc_dt::sc_logic> eoc; In processing function, when I assign it a value '1' like below eoc = '1'; I get following error message A2D.cpp: In member function ‘virtual void a2d_nbit::processing()’: A2D.cpp:50: error: invalid conversion from ‘char’ to ‘sc_dt::sc_logic_value_t’ A2D.cpp:50: error: initializing argument 1 of ‘sc_dt::sc_logic::sc_logic(sc_dt::sc_logic_value_t)’ I also tried to initialize "eoc" in Initialize function like eoc.initialize('1'); but then my compiler gives me another error as follows A2D.cpp: In member function ‘virtual void a2d_nbit::initialize()’: A2D.cpp:28: error: invalid conversion from ‘char’ to ‘sc_dt::sc_logic_value_t’ A2D.cpp:28: error: initializing argument 1 of ‘sc_dt::sc_logic::sc_logic(sc_dt::sc_logic_value_t)’ could you please suggest me how can initialize and assign sc_dt::sc_logic port ? thanks in advance, Milind.
  25. 2 points
    Hello All, I am modeling A2D that uses a successive approximation algorithm. I have modeled A2D converter in SystemC and SystemC-AMS. But both of the models give me some errors. SC model ends up with infinite loop, and SC-AMS model ends with segmentation fault the models are as follows: SC models: Location of the while loop could be the serious problem. I have tried changing the location in side switch statement, but error persists. //error message: stage 1: start edge stage 1: start edge stage 1: start edge stage 1: start edge stage 1: start edge stage 1: start edge stage 1: start edge ...... infinite loop // SC_A2D.h #include<systemc.h> enum adc_state {input, convert}; SC_MODULE(A2D_module) { sc_in_clk clk; sc_in_clk start; sc_in<double> ain; sc_out<sc_logic> eoc; sc_out<sc_lv<8> > dout; sc_signal <adc_state> status; void conversion_logic(); // void next_state_logic(); SC_CTOR(A2D_module) { SC_CTHREAD(conversion_logic, start.pos()); } }; //SC_A2D.cpp #include <SC_A2D.h> void A2D_module::conversion_logic() { eoc = SC_LOGIC_0; dout = "00000000"; double thresh, Vtemp; sc_lv<8> dtemp; int bit_cnt = 8; status = input; while(bit_cnt > 0) { switch (status){ cout << "begin !!!"; case input: if (start == 1) { cout << "stage 1: start edge" << endl; thresh = 5.0; Vtemp = ain; eoc = SC_LOGIC_0; status = convert; } break; case convert: if (clk == 1) { cout << "stage 2: clk edge" << endl; thresh = thresh/2.0; if (Vtemp > thresh) { cout << "stage 3: Vtemp > thresh" << endl; dtemp[bit_cnt]= '1'; Vtemp = Vtemp- thresh; } else { dtemp[bit_cnt]= '0'; } if (bit_cnt > 0) { cout << "stage 4: bit_cnt > 0" << endl; bit_cnt = bit_cnt - 1; } else { cout << "last stage: conversion" << endl; dout = dtemp; status = input; wait(10, SC_US); eoc = SC_LOGIC_1; } } break; } // end switch } // end while } // end method conversion_logic ------------------------------------------------------------------------------------------------------------- SC-AMS models: which gives segmentation fault // Error message: stage 1: Read Input stage 3: Convert Input stage 1: Read Input stage 2 : start edge stage 3: Convert Input stage 4: clk edge !!! bit_cnt = 7 stage 1: Read Input stage 3: Convert Input stage 1: Read Input stage 3: Convert Input stage 4: clk edge !!! Segmentation fault // A2D.h #include <systemc-ams> #include <systemc> #include <stdio.h> using namespace std; //ref: VHDL-AMS Model of A2D converter given in System designer's guide to VHDL-AMS on page 287 SCA_TDF_MODULE (a2d_nbit) { //port declaration sca_tdf::sca_in<double> ain; // analog input pin sca_tdf::sca_de::sca_in<bool> clk; //clock signal sca_tdf::sca_de::sca_in<bool> start; //clock signal sca_tdf::sca_de::sca_out<sc_dt::sc_logic> eoc; //end of conversion pin sca_tdf::sca_de::sca_out<sc_dt::sc_lv<8> > dout; //digitalized output a2d_nbit(sc_core::sc_module_name nm, double Vmax_ = 5.0, double delay_ = 10.0e-6, int bit_range_ = 8, bool start_x_ = 0, bool clk_x_ = 0): ain("ain"), start("start"),clk("clk"), eoc("eoc"), dout("dout"), Vmax(Vmax_), delay(delay_), bit_range(bit_range_), start_x(start_x_), clk_x(clk_x_){} void set_attributes() { set_timestep(50, sc_core::SC_US); eoc.set_delay(1); } void initialize() { eoc.initialize(sc_dt::SC_LOGIC_0); } void processing(); private: double delay; // ADC conversion time double Vmax; int bit_range; bool clk_x; bool start_x; }; // A2D.cpp void a2d_nbit :: processing() { // double Vin = ain.read(); double thresh; //Threshold to test input voltage double Vtemp; //snapshot of input voltage when conversion starts sc_dt::sc_lv<8> dtemp; //temparary output data enum state {input, convert}; int bit_cnt; state status = input; switch(status) // ref: systemC state machine example in SystemC user guide on page 171 { case input : cout << "stage 1: Read Input" << endl; if((start == true) && (start_x == false)) //if (start == true) { cout << "stage 2 : start edge" << endl; bit_cnt = bit_range; thresh = Vmax; Vtemp = ain; eoc = sc_dt::sc_logic('0'); } case convert: cout << "stage 3: Convert Input" << endl; if ((clk == true) && (clk_x == false)) //if (clk == true) { cout << "stage 4: clk edge !!!" << endl; thresh = thresh/2.0; if (Vtemp > thresh) { dtemp[bit_cnt]= '1'; Vtemp = Vtemp - thresh; } else { dtemp[bit_cnt]= '0'; } if (bit_cnt > 0) { bit_cnt = bit_cnt - 1; cout << " bit_cnt = " << bit_cnt << endl; } else { dout = dtemp; eoc = sc_dt::sc_logic('1'); status = input; } break; } default: break; } // end switch start_x = start; clk_x = clk; } ---------------------------------------------------------------------------------------------------------------- // voltage source: dummy_source.h #include<systemc-ams> #include<systemc> #include<iostream.h> #include<fstream.h> using namespace std; SCA_TDF_MODULE (dummy_src) { // sca_tdf::sca_de::sca_out<double> output; sca_tdf:: sca_out<double> output; ifstream infile; double val; dummy_src(sc_core::sc_module_name): output("output"){} void set_attributes() { set_timestep(50, sc_core::SC_US); infile.open("datalog.txt"); } void processing () { if (infile >> val) { output.write(val); } else { output.write(0.0); } } }; ------------------------------------------------------------------------------------------------------------- // top_level_entity : interface.h #include<systemc-ams> #include<systemc> #include<A2D.h> //#include<SC_A2D.h> #include<dummy_source.h> using namespace std; using namespace sc_core; SC_MODULE (interface2) { // A2D_module a2d; a2d_nbit a2d; dummy_src input_vtg; sc_core::sc_clock clk1; sc_core::sc_clock start1; SC_CTOR(interface2) :in("in"), out("out"), a2d("a2d"), input_vtg("input_vtg"), clk1("clk1", 100, sc_core::SC_US, 0.5), start1("start1", 200, sc_core::SC_US, 0.5), eoc("eoc") { input_vtg.output(in); a2d.ain(in); a2d.start(start1.signal()); a2d.clk(clk1.signal()); a2d.eoc(eoc); a2d.dout(out); } public: // sc_core::sc_signal <double> in; sca_tdf::sca_signal<double> in; sc_core::sc_signal<sc_dt::sc_lv<8> > out; sc_core::sc_signal<sc_logic> eoc; }; // top_level_entity: interface2.cpp #include<systemc-ams.h> #include<systemc.h> #include<iomanip> #include<interface2.h> int sc_main(int argc, char* argv[]) { interface2 if2_dut("if2_dut"); sca_util :: sca_trace_file* atfs = sca_util :: sca_create_tabular_trace_file("if2.dat"); sca_util :: sca_trace(atfs, if2_dut.clk1, "\tCLK"); sca_util :: sca_trace(atfs, if2_dut.start1, "\tSTART"); sca_util :: sca_trace(atfs, if2_dut.in, "\tINPUT"); sca_util :: sca_trace(atfs, if2_dut.out, "\tOUTPUT"); sca_util :: sca_trace(atfs, if2_dut.eoc, "\tEOC"); sc_start(400, SC_US); sca_util :: sca_close_tabular_trace_file (atfs); return 0; } -------------------
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