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  1. 8 points
    Admin

    Welcome!

    Welcome to the Accellera Systems Initiative forums. Please register to start new topics or reply to existing topics. We have resently migrated our UVM forums from UVMWorld to this site. If you were registered on the previous UVM forum site, you should be able to log into the forums using your username and password from the UVMWorld forums. If you had an account on both the UVMWorld forums and the Accellera forums and these accounts used the same email address, then log in with the username and password of the forums.accellera.org account, not your UVMWorld account. If you do not remember your password, you may reset it. If you have any questions about using the forums, click the Help button at the bottom of any forum page. If you need any help with your account and you are logged into the site, click the Messenger icon (a letter) in the upper right of your screen, click Compose New, enter “admin” in the Recipient’s Name field, compose your message, and then click Send. You may also send an email to admin@lists.accellera.org. Thank you, Accellera Systems Initiative
  2. 7 points
    India SystemC User Group Conference (ISCUG) A platform to discuss the SystemC based next generation methodologies for design and verification of Electronics Systems (Semiconductor Chips + Embedded Software) Tutorial Day: April 14, 2013 (Sunday) Conference Day: April 15, 2013 (Monday) Venue: Noida, India Register for the event at www.iscug.in. Early bird discount ends on February 28th, 2013. To receive regular updates about the event, register your email at www.iscug.in and follow www.facebook.com/iscug. For sponsorship opportunities, contact info@iscug.in About ISCUG The India SystemC User's Group (ISCUG) organization aims to accelerate the adoption of SystemC as the open source standard for ESL design. ISCUG provide a platform to share the knowledge, experiences and best practices about SystemC usage. ISCUG organize an annual conference which provides a platform for the SystemC beginners, the SystemC experts, ESL managers and the ESL vendors to share their knowledge, experiences & best practices about SystemC usage. The event will also be useful for: SoC Architects involved in architectural exploration, performance optimization, power optimization etc.. Embedded software engineers who want to explore usage of Virtual Platforms for embedded software development Chip verification engineers who want to explore SystemC based verification methodologies Chip design engineers who want to explore SystemC as the language for chip design at higher abstraction level The event is designed on the pattern of similar events happening worldwide: NASCUG, ESCUG, Japan SystemC Forum, etc. Participate You may participate in ISCUG as a speaker. Submit your abstract at www.iscug.in before February 15, 2013. The abstract will be reviewed by the technical review committee; the committee reserves the right to make final decision on speaker selection. You may present a topic related to SystemC modelling, covering virtual platforms, transaction-level modeling, high-level synthesis, SystemC-AMS, modeling for performance analysis, modellng for architectural exploration, SystemC-based SoC verification methodology, or any other topic related to SystemC modeling. You may also present a success story of SystemC adoption in your company. Tutorial Day: There will be a full day of tutorials running in parallel. To participate as a speaker, send details to info@iscug.in. First Half (Before Noon): SystemC and TLM 2.0 Introductory Tutorial Second Half (After Noon): Two/three tracks in parallel (details yet to be finalized) Advanced modeling techniques Virtual platforms for embedded software development and pre-silicon HW/SW co-verification High-level synthesis using SystemC SystemC-based verification methodologies Contact Web: www.iscug.in Email: info@iscug.in
  3. 6 points
    GRENOBLE, France, March 19, 2013 (at the Design Automation and Test in Europe Conference) - Accellera Systems Initiative, an independent non-profit organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards for design and verification, today announces completion of the SystemC® Analog /Mixed-Signal(AMS) 2.0 extensions. SystemC AMS 2.0 is an industry-driven mixed-signal standard for electronic system-level design. The SystemC AMS 2.0 language reference manual (LRM) is available for download ... View the full article: http://www.accellera.org/news/pr/view?item_key=88aa269bcefcfb819e6daf9d73cdca118d3fce5a
  4. 6 points
    Napa, California, USA - February 14, 2012 - Accellera Systems Initiative, the not-for profit organization dedicated to create, support, promote, and advance system-level design, modeling, and verification standards for use by the worldwide electronics industry, will host its annual Accellera Systems Initiative Day on Monday, February 25. The day-long event kicks off the View the full article: http://www.accellera.org/news/pr/view?item_key=07fecbd19a605a7a27dbe42d8e86fe2ae56f46e8
  5. 6 points
    David Black

    Deleting dynamic objects

    You are correct that SystemC does not automatically delete objects. The reason many coders ignore destructors for SystemC modules/objects is several fold: sc_object's (which includes sc_module's, sc_port's, sc_signal's, sc_prim_channel's, etc...) are created during elaboration and would not need to be destructed until the end of simulation when typically a SystemC program simply exits. Thus the operating system will mop up for you. For example: int sc_main(int argc, char* argv[]) { top_module top_instance("top_instance); //< Construct the design hierarchy aka elaborate sc_start(); //< run the simulation return 0; //< exit the simulator and allow OS to clean up } SystemC coders are somewhat lazy and given the above example rationalize it away This is how they were taught (sad but true) That stated, it is probably worth noting that this situation may not always be the case, and some SystemC coders do write destructors (e.g. myself). It should be noted that in a co-simulation environment, the assumption of exiting after simulation may not be true. A vendor simulator might even presume to restart a simulation. Thus I argue it is better to create destructors as good C++ programming habit. TIP: Use the C++11 std::unique_ptr<T> instead of raw pointers. Assumes you can use this class. For older versions of C++, you might consider std::auto_ptr<T>, which is deprecated as I understand it.
  6. 5 points
    Do design and verification engineers care about EDA standards? If the Accellera Systems Initiative "Town Hall" meeting at DVCon 2013 Feb. 25 is any indication, the answer is an emphatic yes. A packed audience attended a lively, hour-long meeting in which non-stop questions were answered by Accellera and IEEE standards developers. - Published by Cadence Industry Insights Blo ... View the full article ...
  7. 5 points
    apfitch

    b-transport interface

    Hi Reza, The idea of the quantum is that a process does *not* give up to the scheduler until it decides enough local time has passed. For instance, imagine the current time (as returned by sc_time_stamp()) is 1000ns. My initiator has a local sc_time variable t. I initialise t to e.g. 10 ns. An initiator thread executes b_transport(tx, t); That means my local time is now 1010ns (but sc_time_stamp() has not changed, and no other process has run). The target which implements b_transport, now updates t by 100ns i.e. t now contains 110ns. In other words, the target is "pretending" it took 100ns to process my request, and my local "pretend" time is 1110ns. I can then call b_transport again with t = 110 + 10 = 120 ns; The target returns with 220 ns; and so on. So in answer to one of your questions, yes there can be many calls to b_transport within a quantum. Let's now suppose the global quantum is set to 500 ns. Eventually, my local time offset is greater than 500 ns. At that point my initiator calls wait(), and another initiator can run. SystemC time is still at 1000 ns, sc_time_stamp() hasn't changed. The second initiator runs sending calls back and forth until its local time offset exceeds the global quantum. It then calls wait(). Eventually all initiators have run and suspended. sc_time_stamp() increases, and off we go again. Now to keep track of that yourself would be possible, but boring to write the code - so in tlm_utils there is a utility called the tlm_quantum_keeper. The idea is that each initiator has its own tlm_quantum_keeper instance, and that's what keeps track of the local time offset. So the answer to "who manages the time" is either "you do - good luck!". Or use tlm_utils::tlm_quantum_keeper (much easier). In your third example, the idea of the delay parameter is that this represents the offset from systemc time (sc_time_stamp()). In my description above, I assumed the target did *not* call wait. However if the target *does* call wait, then the offset must be reset to 0 ns, because sc_time_stamp() has increased. I hope this helps, regards Alan P.S. I suppose I should really try and sell you a training course http://www.doulos.com/content/training/systemc_tlm2.php
  8. 4 points
    The first video series Introducing What's New in UVM 1.2 is out. Also, here is the UVM 1.2 Class Reference This video series covers the changes and new features introduced in UVM 1.2. It is intended for engineers who are already somewhat familiar with UVM. The series comes with CODE EXAMPLES THAT WORK. That's right, real working code and not just a snippet on a slide. The series has the following parts, covering different areas of UVM 1.2 changes. Recommend viewing in 720p quality or higher. uvm_object must have constructor code example Config DB uvm_enum_wrapper code example set_config code example Objections objections code example set_automatic_phase_objection code example Sequences sequence code example uvm_integral_t type uvm_integral_t code example Reporting (major changes) reporting code example Phasing phasing code example Factory extending factory code example parametrized uvm_event uvm_event code example Transaction recording (coming soon) I hope you find it useful. Let me know what other topics you'd like to see. Note: The videos are based on UVM 1.2 release candidate. I do not expect the features covered in the series to change for the final release. The above code examples will always work. If needed, they will be updated for the final UVM 1.2 release.
  9. 4 points
    San Jose, California, USA, DVCon-21 February 2013-Accellera Systems Initiative (Accellera) announced today that Janick Bergeron, a member of the Verification Intellectual Property (VIP) Technical Subcommittee (TSC), is the recipient of the second annual Accellera Technical Excellence Award. The award is being presented at the Design & Verification Conference (DVCon) on Accellera Systems Initiative Day, February 25, 2013 at the DoubleTree Hotel in San ... ... View the full article: http://www.accellera.org/news/pr/view?item_key=0187f877445369468801500478e7a4e264ddad0e
  10. 4 points
    "Accellera Systems Initiative has released the version 2.3.0 of its SystemC open source proof-of-concept library. The offering comes free of charge to the global electronic design community, the organization noted. ... View the full article ...
  11. 4 points
    "This week, Accellera Systems Initiative is announcing a new version of its SystemC library, Version 2.3 to be exact. There hasn't been a new version since way back in 2005 with Version 2.1 (albeit 2.2, a bug-fix release, was published in 2006), so this is the culmination of a lot of hard work." - Published by EDACaf ... View the full article ...
  12. 3 points
    Oh, there seems to be still an issue in 2.3.1, you should change the circular_buffer::clear function to template < typename T > void circular_buffer<T>::clear() { for( int i=0; i < used(); i++ ) { // buf_clear( m_buf, i ); // << BUG HERE buf_clear( m_buf, (m_ri + i) % m_size ); // This should(tm) be correct } m_free = m_size; m_used = m_ri = m_wi = 0; } Thanks for reporting. I'll take this to the Language Working Group to make sure a fix will be included in the next release of the proof-of-concept simulator. (I would still recommend to upgrade to 2.3.1... ) Greetings from Duisburg, Philipp
  13. 3 points
    The link order is incorrect. The dependencies are resolved from right to left. Your Makefile should say: # list SCV before SystemC LIBS = -lscv -lsystemc -lm # local objects first, then the required libraries $(TARGET): $(OBJS) $(CC) -o $@ $(LIBDIR) $(OBJS) $(LIBS) As a side note: For C++ applications, you should prefer the variables CXX (for the C++ compiler) and CXXFLAGS (for the compiler flags). CC and CFLAGS are intended for C projects. Secondly, I would recommend not to define DEBUG_SYSTEMC in user code. hth, Philipp
  14. 3 points
    Hi. Yes. A port does not hold a value. Whenever you access a port (read or write) you actually access the channel or signal bound to it. So, the port behaves like that signal. (But you should not write to an input port ) Greetings Ralph
  15. 3 points
    I'm seeing the uvm_object get_inst_id() function not returning unique, new IDs for new objects that I create. More specifically, it's returning a repeating cycle of a few different IDs. Looking under the hood at uvm_object.svh it's a pretty trivial mechanism so I can't see why it isn't working. Also, in a derived class I created I mimicked the same mechanism and my mechanism works fine. Test case and example output is below. Note that the static instance count value seems to increment nicely as expected but the instance ID values seem to bear no relation to that count and repeat every 6 objects. Am I missing something really obvious here or is this a possible bug. I see this using UVM 1.1d downloaded from Accellera. ////////////////////////////////////////////////////////////////////////////////////////////////////////////// class my_object_t extends uvm_object; static int next_id; int my_id; function new (string name="my_object"); super.new(name); my_id = next_id++; endfunction : new `uvm_object_utils(my_object_t) endclass begin my_object_t my_object; for (int i = 0; i < 100; i++) begin my_object = new(); `uvm_info("", $sformatf("my object inst id is %d (0x%0x) or %0d, inst count is %d (0x%0x) or %0d", my_object.get_inst_id(), my_object.get_inst_id(), my_object.my_id, my_object.get_inst_count(), my_object.get_inst_count(), my_object.next_id), UVM_LOW) end end UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is 72135 (0x119c7) or 0, inst count is 9585 (0x2571) or 1 UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is 72122 (0x119ba) or 1, inst count is 9586 (0x2572) or 2 UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is 581 (0x245) or 2, inst count is 9587 (0x2573) or 3 UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is 72126 (0x119be) or 3, inst count is 9588 (0x2574) or 4 UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is 72120 (0x119b8) or 4, inst count is 9589 (0x2575) or 5 UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is 69783 (0x11097) or 5, inst count is 9590 (0x2576) or 6 UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is 72135 (0x119c7) or 6, inst count is 9591 (0x2577) or 7 UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is 72122 (0x119ba) or 7, inst count is 9592 (0x2578) or 8 UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is 581 (0x245) or 8, inst count is 9593 (0x2579) or 9 UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is 72126 (0x119be) or 9, inst count is 9594 (0x257a) or 10 UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is 72120 (0x119b8) or 10, inst count is 9595 (0x257b) or 11 UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is 69783 (0x11097) or 11, inst count is 9596 (0x257c) or 12 UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is 72135 (0x119c7) or 12, inst count is 9597 (0x257d) or 13 UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is 72122 (0x119ba) or 13, inst count is 9598 (0x257e) or 14 UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is 581 (0x245) or 14, inst count is 9599 (0x257f) or 15 UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is 72126 (0x119be) or 15, inst count is 9600 (0x2580) or 16 UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is 72120 (0x119b8) or 16, inst count is 9601 (0x2581) or 17 UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is 69783 (0x11097) or 17, inst count is 9602 (0x2582) or 18 UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is 72135 (0x119c7) or 18, inst count is 9603 (0x2583) or 19 UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is 72122 (0x119ba) or 19, inst count is 9604 (0x2584) or 20 UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is 581 (0x245) or 20, inst count is 9605 (0x2585) or 21 UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is 72126 (0x119be) or 21, inst count is 9606 (0x2586) or 22 UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is 72120 (0x119b8) or 22, inst count is 9607 (0x2587) or 23 UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is 69783 (0x11097) or 23, inst count is 9608 (0x2588) or 24 UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is 72135 (0x119c7) or 24, inst count is 9609 (0x2589) or 25 UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is 72122 (0x119ba) or 25, inst count is 9610 (0x258a) or 26 UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is 581 (0x245) or 26, inst count is 9611 (0x258b) or 27 UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is 72126 (0x119be) or 27, inst count is 9612 (0x258c) or 28 UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is 72120 (0x119b8) or 28, inst count is 9613 (0x258d) or 29 UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is 69783 (0x11097) or 29, inst count is 9614 (0x258e) or 30 UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is 72135 (0x119c7) or 30, inst count is 9615 (0x258f) or 31 UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is 72122 (0x119ba) or 31, inst count is 9616 (0x2590) or 32 UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is 581 (0x245) or 32, inst count is 9617 (0x2591) or 33 UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is 72126 (0x119be) or 33, inst count is 9618 (0x2592) or 34 UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is 72120 (0x119b8) or 34, inst count is 9619 (0x2593) or 35 UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is 69783 (0x11097) or 35, inst count is 9620 (0x2594) or 36 UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is 72135 (0x119c7) or 36, inst count is 9621 (0x2595) or 37 UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is 72122 (0x119ba) or 37, inst count is 9622 (0x2596) or 38 UVM_INFO @ 0 ns: uvm_test_top.tb.c [] my object inst id is 581 (0x245) or 38, inst count is 9623 (0x2597) or 39
  16. 3 points
    In SystemC, the word "channel" simply means "something that implements an interface" and so can be bound to ports. In that sense, a "channel" doesn't have to be a means of communication. For instance you could have a RAM model that implemented an interface with read and write functions. The extra things you get in SystemC, beyond C++, are the ability to make your system modular with modules and ports; and threads (processes), events and time. Ports are templated with interfaces (classes derived from sc_interface) which specify that the thing bound to the port must provide the required functions. If you look at TLM2, for instance, ports are bound to exports, and the modules with the exports implement the functions that the modules with the ports require. In the original SystemC usage, both an initiator and a target are "a channel" in the sense that they implement an interface. What I'm trying to say is that you don't have to really think about channels at all. You can simply think in terms of interfaces, classes that implement those interfaces, and ports and exports that promote modularity by (in a sense) acting as special pointers with strong type checking. Of course in the SystemC library there are some built-in primitive channels, which have the special feature that they follow evaluate-update semantics. But that's just a special case of the more general concept of implementing an interface and accessing implemented methods remotely via ports/exports. So if you don't need the features that ports/exports/modules give you, you don't have to use them. Which is a long way of saying "yes" to your question :-) The main disadvantage of using immediate notify is non-deterministic behaviour. regards Alan
  17. 3 points
    Hello all, For those who were not able to attend the SystemC AMS tutorial at DVCon 2014, the full tutorial is now made available as webcast, including the presentations with voice-over, examples ("labs") and solutions. Visit the following link (free registration required) http://www.accellera.org/resources/videos/amsnextwave We appreciate your feedback and your experience after following this SystemC AMS tutorial. Regards, Martin
  18. 3 points
    dave_59

    conditionnal import package in SV

    The import statement only makes symbols visible inside the scope of the import. Your import statement is inside a generate block and does not make symbols visible after the generate. If you need to select this package globally, it might be better to have two different versions of the same package compiled into separate libraries. Then just select the library you want at compilation time. If the package only contains parameter values, then you might consider using a structure or class type as a container for your parameters instead of a package.
  19. 3 points
    First, before I discuss the problems with SystemVerilog, I would like to point out that you are really missing a much simpler solution to your problem: module top; int farray[10]; //fixed array initial begin foreach (farray[jjj]) begin farray[jjj] = $urandom_range(121,0); end $display("******************************"); foreach (farray[jjj]) begin $display("%0d: %0d",jjj,farray[jjj]); end end endmodule : top With respect to "how many elements does my container have?", try the following. Note that you may need to comment out a few lines since the EDA vendor simulators don't all agree on whether some of these should work, and to be fair, the standard is not entirely clear... module top; byte Fixed_array[3]; byte Dynamic_array[] = {10, 20, 30}; string String = "abc"; byte Queue[$] = {40,50,60}; byte Assoc_array[string] = '{"a":70,"b":80,"c":90}; initial $display("Fixed_array size is %0d", $size(Fixed_array) ); initial $display("Dynamic_array size is %0d", Dynamic_array.size() ); initial $display("String size is %0d", String.len() ); initial $display("Queue size is %0d", Queue.size() ); initial $display("Assoc_array size is %0d", Assoc_array.num() ); // Alternate approach initial $display("$size(Fixed_array ) is %0d", $size(Fixed_array) ); initial $display("$size(Dynamic_array) is %0d", $size(Dynamic_array) ); initial $display("$size(String size ) is %0d", $size(String) ); // May not be legal initial $display("$size(Queue size ) is %0d", $size(Queue) ); initial $display("$size(Assoc_array ) is %0d", $size(Assoc_array) ); // Yet another approach initial $display("$bits(Fixed_array ) is %0d", $bits(Fixed_array) ); initial $display("$bits(Dynamic_array) is %0d", $bits(Dynamic_array) ); initial $display("$bits(String size ) is %0d", $bits(String) ); initial $display("$bits(Queue size ) is %0d", $bits(Queue) ); initial $display("$bits(Assoc_array ) is %0d", $bits(Assoc_array) ); // Strange result endmodule The standard attempts to rationalize away this inconsistency at the bottom of page 45 (85 in the PDF) in the IEEE 1800-2012 standard:[/size][/font][/color][/code] I for one don't entirely agree with this rationalization. The concepts are all closely related and should have been unified to make the coders job easier. Actually, $size() appears to work with most of them.
  20. 3 points
    Philipp A Hartmann

    SystemC pause

    Yes, there is an sc_pause in SystemC (since IEEE 1666-2011 / 2.3.0). By calling this function from within your simulation, you can return to sc_main (see IEEE 1666-2011, Section 4.5.2). Please note that in the context of the SystemC AMS extension, pausing the simulation may be somewhat dangerous, as noted in Section 5.1.1 of the AMS extensions 2.0 LRM: That said, the use cases you have described seem to be blocking in nature. Why not simply call the code to ask for user input directly from the "specified point in the code"? In this case, you don't need to interfere with the simulator directly. NB: sc_halt is not part of IEEE 1666 and is not meant to be used in new code. Greetings from Oldenburg, Philipp
  21. 3 points
    Accellera Day at DVCon Monday, March 3, 2014 8:30am - 7:00pm DoubleTree Hotel, San Jose CA Accellera invites you to a special day dedicated to technical standards at the 2014 Design and Verification Conference. Connect with experts and users as we learn, share, and network on the latest in EDA and IP standards innovations. Tutorial: UVM™ - What’s Now and What’s Next Tutorial: Using UPF for Low Power Design and Verification Lunch Panel and Technical Excellence Award Presentation Tutorial: Case Studies in SystemC™ Tutorial: Experience the Next ~Wave~ of Analog and Digital Signal Processing Using SystemC™ AMS 2.0 Tutorial: OCP: The Journey Continues DVCon Expo - Booth Crawl View full details >
  22. 3 points
    You need to create the ports while the correct instantiation context is established. Since you can't do so during construction of the module, you need to defer it to the 'before_end_of_elaboration()' callback of SystemC. For this matter, you need to temporarily store the signals, in e.g. a vector of pointers. See the following (untested) sketch: SCA_TDF_MODULE(waste) { sca_tdf::sca_in<double> in; // Main 'in' port sc_core::sc_vector< sca_tdf::sca_in<double> > secondary_ins; // prefer sc_vector over vectors of pointers SCA_CTOR(waste) : in("in"), secondary_ins( "secondary_in" ) { } // temporarily store signal pointer void bind(sca_tdf::sca_signal<double> &s) { sc_assert( sc_core::sc_get_status() == sc_core::SC_ELABORATION ); secondary_signals.push_back( &s ); } void processing() { //... } private: // actually do the binding virtual void before_end_of_elaboration() { // create the secondary ports secondary_ins.init( secondary_signals.size() ); // bind the ports for( std::size_t i = 0; i < secondary_ins.size(); ++i ) secondary_ins[i].bind( *secondary_signals[i] ); // cleanup temporary signals secondary_signals.clear(); // be nice and call the base class callback sca_tdf::sca_tdf_module::before_end_of_elaboration(); } // temporarily hold additional inputs during elaboration std::vector< sca_tdf::sca_signal<double>* > secondary_signals; }; Hope that helps, Philipp
  23. 3 points
    Philipp A Hartmann

    suspend/resume

    Yes. Have a look at IEEE 1666-2011, Section 4, especially 4.3.4.2 (sc_start, the starvation policy, and sc_pause). ("suspend" and "resume" are functions for individual SystemC processes, sc_start/sc_pause/sc_stop control the overall simulation). /Philipp
  24. 3 points
    ytakatsukasa

    Could anybody help me with QEMU ??

    Hi Mohit QEMU is an open source software mostly written in C. It emulates different architectures (ARM,MIPS, PPC, and more) from host and can run binaries on it. So you can boot android for arm on x86 PC. As far as I know the typical use cases of QEMU are System Emulator Frontend for Virtualization As a system emulator, android sdk uses QEMU to boot android to let developer check the application on x86 pc not on arm development board. Xilinx Xynq development kit also uses QEMU to run the software for the FPGA on x86 pc. For virtualization, QEMU is used to virtualize x86 pc on x86 pc (or arm on arm) with KVM or XEN. Shorter answer: Yes, Green Socs and TLMu are famous project for it. Iguess there may be similar projects more. Longer answer: QEMU consists of many kinds of processor models and peripheral models, so many tried to use it with SystemC. I also succeeded to boot arm linux on my customized TLMu( QEMU processor model + SystemC peripheral models). IMHO QEMU has 3 difficulties for integrating with SystemC. Building QEMU is sometimes troublesome because of its dependencies on many libraries. QEMU is written in C with gtk-like object system and with so many global/static variables. It is tough to understand and modify the source code. Global variables prevent you from multi-instantiation. QEMU source code is always changing and its speed is fast. It will be a painful work to catch up with the mainline release after you fork QEMU. QEMU is a really really useful software, actually I use it for virtualization and appreciate it. But honestly its source code is not something that I would love to recommend for learning material. I hope you will find a cool way to integrate it with SystemC. Regards, Yutetsu.
  25. 3 points
    Philipp A Hartmann

    problem with constructor

    As the error says (emphasis mine) you need a default constructor (a constructor without arguments) in your case. In the module, you create an instance of 'decimal' without explicitly initializing it in the constructor of 'seprate_digit'. Theoretically, you could use an initializer list: SC_CTOR (seprate_digit) : in("in"), clk("clk"), d("d") // port names -> recommended practice , decimal(0,0,0,0) // <-- explicitly initialize decimal member Since you use 'decimal' as a signal type, you'll definitely need a default constructor. This could look like the following decimal() /* : dec0(), dec1(), dec2(), dec3() */ // optional, as sc_int has an explicit default constructor {} Secondly, you'll need to define more helper functions to use sc_signal with your own data types, see http://www.doulos.com/knowhow/systemc/faq/#q1 Greetings from Oldenburg, Philipp NB: Why do you post the question three times in 10 minutes? ;-)
  26. 3 points
    apfitch

    systemC synthesis guidlines

    Hi Mohit, 1. The important issue is not the language, but the technology. Behavioural synthesis tools generally deduce a combination of state machines (for control) and datapath (for signal processing). The key thing is that you as a designer do not have to write the micro-architecture yourself. Hence behavioural synthesis is potentially more productive than standard RTL synthesis. That argument is language independent. A behavioural VHDL tool would be more productive than an RTL VHDL tool. Writing RTL in SystemC would be no more productive than writing RTL in VHDL or Verilog. So your question "why do we require SystemC sythesis when we have HDL synthesis" would be better as "why do we need behavioural synthesis rather than RTL synthesis". And the answer is you only need it if it's better for you in some way (faster time-to-market for instance). No-one is forcing you to use behavioural synthesis :-) 2. I don't know if SystemC synthesis tools are interoperable. 3. How come tools exist even though the synthesis standard is a draft? EDA vendors are free to ignore standards :-) Standards only get adopted (and developed) if EDA vendors and users can see value in those standards. So I guess no-one is motivated to finish the synthesis standard. The key thing about the synthesis standard (as opposed to a language standard) is it's trying to guide how a tool may interpret SystemC code. EDA vendors see that as a legitimate area of product differentiation. The same thing happened with VHDL 1076.6 - the vendors essentially ignored it. 4. You may mix synthesisable and non-synthesisable code, you just have to hide the code using the pre-processor or meta-comments. The same is true in VHDL and Verilog - you can include non-syntheisable code, but it is typically hidden using meta-comments, e.g. -- synthesis translate_off code that won't synthesize goes here -- synthesis translate_on regards Alan
  27. 3 points
    apfitch

    Why SystemC and who uses it ???

    Hi Karandeep, the main usage of SystemC is in design of large SoC. As such, it is mainly used by large semiconductor companies. Typically such a company may be developing a large chip (very large!). That causes a number of problems How to concurrently develop software and hardware? How to start writing software drivers before the RTL design is finished? How to develop a reference model to be used in with Testbench Automation/Constrained Random Verification environments? How to build and re-use IP models for use in a high level model? (otherwise every company has to build processor models, bus fabric models etc from scratch). If developing a completely new chip, how to analyse bus bandwidths, data flows and so on - especially with multiple processors competing for bus resource. SystemC allows a company to attack all these problems - by building a model with accurate register modelling, the model may be used for software device driver development. Typically using very fast processor models and loosely timed styles, that model can boot multiple pieces of software on processor models at high speed. With some refinement, a similar model can be used as a reference for TBA/CRV. You need a reference model, so why not re-use it? For architectural analysis an approximately timed model is better suited - but remember you might not need it if you are refining an existing platform rather than starting from scratch. For re-usable models - that's the point of TLM2, to create a standard API to allow exchange of models. Existing APIs (SCML, TAC etc) can gradually migrate to a standard, promoting re-use. Finally why SystemC? Why not use SystemVerilog; or Java; or Python; or Haskell; or <fill in your favourite language here>? There are many factors, some practical, some political, some historical. In my opinion the main factors are/were 1. System Architects speak C++ / Excel / Word /Matlab. They don't speak Verilog/SystemVerilog/VHDL 2. SystemC started in 1999 3. EDA vendors got behind SystemC and developed tools to allow virtual platforms to be built I hope that helps, regards Alan P.S. Regarding finding references / information/ facts, the key point to remember is that the world of SoC/VLSI design is small. There just aren't many companies with the resources to develop large chips; and within those companies, there just aren't many system architects / modellers. In a typical large chip development they'll probably be many software engineers - probably considerably more than hardware engineers; within hardware, they'll be a few back-end people; a reasonable number of RTL designers; a similar or larger number of verification engineers; and perhaps 1 system architect. So SystemC just isn't used by large numbers of people, compared the Verilog/VHDL/SystemVerilog.
  28. 3 points
    Hello all, Accellera Systems Initiative annouced the release of the SystemC AMS 2.0 standard. The AMS 2.0 standard is available as Language Reference Manual and can be downloaded here: http://www.accellera.org/downloads/standards/systemc Note that this standards update does not contain the user's guide. The AMS working group is working hard to release this document in the future. Now that AMS 2.0 is available, we anticipate that EDA companies and/or research institutes are getting inspired to make a proof-of-concept compatible with this standard. This means that today there is no simulation platform available, but we expect in the future it will become available. Also ask your preferred EDA vendor or partner when SystemC AMS 2.0 gets integrated in the tool and flow. Feel free to post your questions or remarks on the new SystemC AMS 2.0 standard in this forum. Regards, Martin Barnasconi AMS working group chair
  29. 3 points
    David Black

    SystemC in Visual Studio 2012

    Try: 1. Installed Visual C++ 2012 Express Edition (Note - won't work on XP only Windows 7/8) 2. Download Systemc-2.3.0.tgz 3. uncompress systemc-2.3.0.tgz 4. Assuming in c:\systemc-2.3.0 5. copy msvc80 to msvc11 (optional, but helps if you attempt to run regressions) 6. Run Visual C++ 2012 EE and open msvc11\systemc\systemc.sln 7. Upgrade is offered - click OK 8. Menu Build > Build Solution Build failed due to warning 4005 Edit sc_cmnhdr.h line 75 and add a test for _MSC_VER == 1200 as follows: // MSVC6.0 for() scope bug #if defined(_MSC_VER) && (_MSC_VER == 1200) #define for if( false ); else for #endif Now it should build. 9. Add an environment variable SYSTEMC set to c:\systemc-2.3.0\ 10. Set library, src, include paths as for Visual C++ 2010 Note: to find the property pages, load in a project (e.g. ex6 from the course). Then do View > Other Windows > Property Manager Expand the project name until you find Debug | Win32 > Microsoft.CPP.Win32.user and set the include and library directories to $(SYSTEMC)\src $(SYSTEMC)\msvc11\systemc\debug
  30. 3 points
    San Jose, Calif., USA, 25 February 2013 (at the 2013 Design and Verification Conference) -- Accellera Systems Initiative (Accellera) announce today they have once again partnered with the IEEE Standards Association (IEEE-SA), a globally recognized standards-setting body within the IEEE, to deliver a leading electronic design and verification standard to engineers and chip designers worldwide. The revised version of the IEEE 1800 "Standard ... ... View the full article: http://www.accellera.org/news/pr/view?item_key=fb54cca2b7ac0cdcfd6ffacb85692f1a808adab0
  31. 3 points
    apfitch

    SystemC Guides for Beginners

    On our website there's a tutorial and a number of videos and examples of TLM2 and SystemC (see www.doulos.com/knowhow/systemc and www.doulos.com/knowhow/systemc/tlm2), though I must admit the tutorial is quite hardware orientated. There used to be a tutorial on the Forte Design Systems website, but I can't find it any more. I would recommend downloading the latest standard (IEEE 1666-2011) via http://www.accellera.org/downloads/ieee/ I certainly would *not* recommend either the 2.0 user guide or the 2.0.1 reference manual, they are very out-of-date. To paraphrase someone, every time I see sc_bit I reach for my revolver :-) Probably the best general book is "SystemC from the Ground Up" by David C Black, Jack Donovan, Bill Bunton and Anna Keist. regards Alan
  32. 3 points
    The old syntax sc_start(int) was deprecated when we removed the sc_set_default_time_unit(sc_time) concept. Your choices for sc_start are limited to sc_start(void), sc_start(sc_time) and sc_start(double),sc_time_unit).
  33. 3 points
    Following are European SystemC Users' Group events at the DATE Conference 2013 in Grenoble, France. 27th European SystemC Users' Group Meeting Tuesday March 19th, 2013 6:30pm - 9:30pm Room TBA Join the Accellera update and town hall meeting around Accellera technologies and standards. We give insights into their influence and requirements for future design strategies. More information, including registration and the final program, will be available at: http://www.ti.uni-tu...10.0.html?&L=0/. European SystemC Users' Group Workshop ESL -- Putting the Pieces Together: Integrating SystemC Design and Verification with AMS and Algorithm Design Friday March 22nd, 2013 8:30am - 4:50pm Room TBA This full-day workshop is focused on the integration of SystemC design and verification with AMS and algorithm design. It gives deep insights on how techniques may collaborate and converge. These topics are gaining more and more interest because a seamless integration of all relevant design and verification techniques is crucial. Besides digital hardware design, this is substantially important for the areas of algorithm and AMS design. The keynote from STMicroelectronics discusses the challenges of design flow integration in multi physical domain applications. The workshop includes four invited sessions from TU Kaiserslautern, NXP, Fraunhofer IIS, and Bosch -- providing knowledge about the core technologies, their application, and integration into ESL design flows. The core session’s part is complemented by an interactive discussion with the audience. This session is organized in town hall meeting style. This event requires registration. For an agenda and to register, see http://www.date-conf...nce/workshop-w1.
  34. 3 points
    NAPA, Calif. - November 15, 2012 - Nominations are being accepted now through Friday, January 18 for the 2013 Technical Excellence Award sponsored by Accellera Systems Initiative (Accellera). The Award recognizes outstanding contributions in the creation of electronic design automation (EDA) and intellectual property (IP) standards by a member of an Accellera technical committee. Standards created by Accellera are contributed to the IEEE Standards Association ... ... View the full article ...
  35. 3 points
    Hi Sumit, header guards won't necessarily help. They stop two header files being included sequentially - but if you have a function *body* in the header, and include that header in two independent files, you'll still get multiple definitions at link time. My guess is that Timmy is #including a gnoise.cpp. In that case the fix is to make a gnoise.h with the function prototype, with your header guards of course, and include the .h not the .cpp, regards Alan
  36. 3 points
    Napa, Calif., USA, 16 July 2012 - Accellera Systems Initiative announces the release of version 2.3.0 of its SystemC open source proof-of-concept library, now available at no charge to the worldwide electronic design community. Compatible with the newly revised IEEE 1666 "Standard SystemC Language Reference Manual," announced by the IEEE Standards Association in November 2011, version 2.3.0 provides a number of important new features, ... ... View the full article ...
  37. 2 points
    ralph.goergen

    SystemC-2.3.1a clang build fail

    Hi. There seems to be a problem with the '#if defined' expressions. MSYS gcc and clang define _WIN32, and in combination with using pthreads, SC_USE_PTHREADS is defined as well. Could you please evaluate possible fixes? E.g. adding '!defined(SC_USE_PTHREADS)' in line 33 of sc_cor_fiber.h? And could you please try with the public review version of SystemC 2.3.2 as well (http://www.accellera.org/downloads/drafts-review)? If this works, I can try to forward the issue to the SystemC developer working group. Greetings Ralph
  38. 2 points
    It's not sufficient that all the blocks work properly, because it might be the case that they aren't properly connected to each other. Outputs from some block are left hanging and the corresponding inputs are tied to some values. Cascaded block level checks can't really find this, if your observation points for each block level environment are its corresponding design block. Example: A can start read or write transactions, but the direction signal doesn't get passed to B, where it's tied to read. The A or B env checks won't fail, but the whole system is buggy.
  39. 2 points
    mastrick

    randomize() with inside syntax

    Also, you might want to keep your randomize() call outside the assert(). Otherwise, simulators may not call the randomize at all if you disable assertions (e.g. to temporarily work around a problem). You can assign the return from randomize() to a variable and then assert that variable.
  40. 2 points
    dave_59

    walk thru an enumeration

    You can use a do-while loop: module top; //typedef enum {alpha=0, beta=1, gamma=2, delta=3, epsilon=4} greek; //to show default assignments typedef enum {alpha, beta, gamma, delta, epsilon} greek; greek letters; initial begin $display("****** Walk thru an enumeration example. ***********"); letters = letters.first; do begin $display(" %0d *** %0s", letters, letters.name); letters = letters.next; end while (letters != letters.first); end endmodule : top
  41. 2 points
    Hi UVM and SystemVerilog users, I've stumbled upon a particular pattern of writing a "utility" class, which I have called "mixin". class derived_class#(type BASE=base_class) extends BASE; .... endclass : derived_class This pattern was inspired by some C++ Boost code I saw, where the base class is templated. The reasoning was that under some compilers, multiple inheritance had higher overhead than chains of inheritance (specifically, an "empty" base class might be allocated the minimum size, so multiple inheritance would increase the size of the object, but if you used a chain of inheritance and a derived class in the chain was "empty" (i.e. did not add any data members), it would not increase the object size). So instead of inheriting from multiple C++ classes, you'd typedef a class like foo<bar<nitz> > and derive from that. Since SystemVerilog has no multiple inheritance, I thought this pattern would be appropriate for use in SV, to at least ease some of the "oh no SV has no multiple inheritance oh no" pain. I've defined a simple utility class, utility::slave_sequence_item (utility is a package) defined like so: class slave_sequence_item#(type BASE=uvm_sequence_item) extends BASE; local uvm_barrier wait_barrier_; local uvm_barrier fin_barrier_; `uvm_object_param_utils_begin(utility::slave_sequence_item#(BASE)) `uvm_field_object(wait_barrier_, UVM_ALL_ON) `uvm_field_object(fin_barrier_, UVM_ALL_ON) `uvm_ojbect_utils_end function new(string name=""); super.new(name); wait_barrier_ = new("wait_barrier_", 2); fin_barrier_ = new("fin_barrier_", 2); endfunction // to be called by sequence task wait_for_transaction; wait_barrier_.wait_for; endtask task finish_transaction; finish_barrier_.wait_for; endtask // to be called by driver task indicate_transaction; wait_barrier_.wait_for; finish_barrier_.wait_for; endtask endclass : slave_sequence_item Basically, this slave sequence item class adds three new methods. By default, you just derive from utility::slave_sequence_item. But if you already have an existing sequence item type derived from uvm_sequence_item, you just do typedef utility::slave_sequence_item#(my_sequence_item) my_slave_sequence_item; and the added methods and variables will get "mixed in" the my_slave_sequence_item type. What do you think? I've tested it on Cadence IUS10.20-s103, and it seems to work properly. From my understanding of the IEEE standard, the above is not specifically disallowed (but then it might not be well supported on actual simulators).
  42. 2 points
    San Francisco, Calif., June 3, 2014 (at the Design Automation Conference) -- Accellera Systems Initiative (Accellera), an independent non-profit organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards, announces it has developed new verification and design modeling extensions for its Verilog-AMS standard. Verilog-AMS provides powerful structural and behavioral modeling capabilities for mixed-signal designs in which the ... ... View the full article ...
  43. 2 points
  44. 2 points
    it looks like you instantiated a sca_core::sca_module (or you derived from this class) - this is not possible. You can only derive own modules from sca_tdf::sca_module or of course you can instantiate the pre-defined sca_eln/sca_lsf modules. In SystemC-AMS it is not allowed to derive own modules from sca_core::sca_module (see LRM). best regards Karsten
  45. 2 points
    That is an obsolete document, I do not recommend using it. It was never a standard. Use the IEEE 1666-2011 standard. If you read that standard, there is a list of deprecated features, including on page 583 the information that default time unit is deprecated. n) Default time units and all the associated functions and constructors, including: 1) Function sc_simulation_time 2) Function sc_set_default_time_unit 3) Function sc_get_default_time_unit 4) Function sc_start(double) 5) Constructor sc_clock(const char*, double, double, double, bool) No, there is no default time unit. You are quoting an obsolete document which was never a standard. However there is a default constructor for sc_clock, which sets the default clock *period* to 1 ns. So if you wrote sc_clock clock; // name is "clock_0", period 1, SC_NS, posedge_first true, delay to first edge 0, SC_NS See the LRM description of sc_clock, p149ff. There is a default time *resolution* of 1 ps. What that means is if you say wait(1.0001, SC_NS); you will lose the fractional part of the time delay as it is less than 1 ps. You can change the *resolution* using sc_set_time_resolution() (see page 102). Yes that works. No that doesn't work. You still have to use 20, SC_US with SystemC 2.1, 2.2, 2.3 (LRM 1666-2005 1666-2011). There is no default time unit. Don't mix up the time resolution (the minimum representable time value) and default time unit (a deprecated feature of SystemC before it was standardised). regards Alan
  46. 2 points
    apfitch

    benifits of sc_export over sc_port

    You have to parameterize the export by the interface. So if you have two interfaces, and you want them to be exported by a single export, you'd have to create a derived class. For instance class tom_if : virtual public sc_interface { public: virtual void tom() = 0; }; class dick_if : virtual public sc_interface { public : virtual void dick() = 0; }; class harry_if : virtual public sc_interface { public: virtual void harry() = 0; }; class mychan : public tom_if, public dick_if, public harry_if { void tom() { // implementation of tom() } void dick() { // implementation of dic() } void harry() { // implementation of harry() } }; Now you can write exports such as class mod { public: sc_export<tom_if> e_tom; sc_export<harry_if> e_harry; mychan chan; SC_CTOR(mod) { e_tom.bind(chan); e_harry.bind(chan); } }; If you want a combined interface, then you could write class tom_dick_if : virtual public tom_if, virtual public dick_if { }; Then write class mychan : virtual public tom_dick_if { public: // blah blah blah }; Then you could declare an export sc_export<tom_dick_if> As I said before, it's worth looking at the code in systemc-2.3.0/src/tlm_core/tlm_1/tlm_req_rsp regards Alan
  47. 2 points
    The answer is that it's an OR. The description of static sensitivity is on page 16 "The sensitivity of a process instance is the set of events and time-outs that can potentially cause the process to be resumed or triggered. The static sensitivity of an unspawned process instance is fixed during elaboration. The static sensitivity of a spawned process instance is fixed when the function sc_spawn is called. The dynamic sensitivity of a process instance may vary over time under the control of the process itself. A process instance is said to be sensitive to an event if the event has been added to the static sensitivity or dynamic sensitivity of the process instance. A time-out occurs when a given time interval has elapsed." By "set of events" it means that any one of those events can cause a process to resume, regards Alan
  48. 2 points
    David Long

    static and dynamic sensitivity

    wait() with no arguments is only used for static sensitivity next_trigger() has similiar functionality to wait() but is only used within sc_method processes, while wait() is only used within sc_thread processes. The main difference is that sc_methods cannot consume time (wait is illegal) so next_trigger (with an argument) overrides any static sensitivity to control when the sc_method will next be called (after it has completed). There might be multiple calls to next_trigger in the same sc_method - the last one to be executed before the function returns is the one that sets the sensitivity for the next call. Regards, Dave
  49. 2 points
    David Black

    async_request_update example

    struct thread_safe_event_if : sc_core::sc_interface { virtual void notify(sc_core::sc_time delay = SC_ZERO_TIME) = 0; virtual const sc_core::sc_event& default_event(void) const = 0; protected: virtual void update(void) = 0; }; struct thread_safe_event_channel : sc_core::sc_prim_channel, thread_safe_event_if { thread_safe_channel(const char* name); void notify(sc_core::sc_time delay = SC_ZERO_TIME); const sc_core::sc_event& default_event(void) const; protected: virtual void update(void); private: sc_core::sc_event m_event; sc_core::sc_time m_delay; }; // The following may be safely called from outside the SystemC OS thread void thread_safe_event_channel::notify(sc_core::sc_time delay) { m_delay = delay; async_request_update(); } const sc_core::sc_event& thread_safe_event_channel::default_event(void) { return m_event; } virtual void update(void) { m_event.notify(m_delay); }
  50. 2 points
    maehne

    Simple AMS examples

    Hello Jens, regarding the late reply due to lack of notification: This is a weakness of the new forum. You have to configure e-mail notifications manually by clicking on your account name on the top right of the web page and then clicking on My Settings. There you can configure to receive e-mail notifications for followed forums and threads. Afterwards, you still have to select the forums and threads to follow. Regarding your actual modeling problem. If you want to model a memristor in SystemC-AMS, then I agree that a TDF-only solution would be preferable. However, then you'll have to make a choice upon model creation on which causality you assume for the Memristor, i.e. how it is operated. Is it driven by a current or a voltage? This will fix its state and output variable. Then, you'll be able to express you memristor equations in a compact TDF model using e.g. an embedded LTF function for the integration of the current and implementing the non-linear M(q(t)) function inside the processing() member function. An implementation combining ELN and TDF will be suboptimal, as it will imply a tight feedback loop between a controlled resistor and a TDF module implementing the non-linear part of the Memristor equations, which has to be broken with a 1 timestep delay. This causes of course a change in the dynamic of your system and in consequence your simulation results will heavily depend on the chosen TDF timestep. Sumit's remarks on SystemC-AMS not being the most suited modeling language for describing circuit-level behavior are valid. LSF and ELN are limited to describing linear (switched) dynamic behavior and trying to model nonlinear behavior with them by combining them with tightly coupled TDF modules leads to suboptimal results. It's a simulation framework intented for the system-level, where most of the circuit level details have been abstracted away to focus on the system architecture and evaluate specifications for whole signal processing and control chains, which contain a significant amount of digital Hw/Sw. In contrast to VHDL-AMS and Verilog-AMS, SystemC-AMS does not offer a nonlinear network MoC, which allows you to solve nonlinear DAEs. Though, Fraunhofer IIS/EAS in Dresden have developed one, which integrates seamlessly into SystemC-AMS, you can check out the publication of Thomas Uhle in SOCC 2010 on it. However, it is not available as open-source. Therefore, VHDL-AMS or Verilog-AMS may still be a more appropriate choice for your needs. Best regards, Torsten
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