Leaderboard

Hello, We have an error in Cadence with UVM compilation of Hello World example, ncsim: *F,NOLWSV: Searching for import subroutine "uvm_hdl_deposit" in default library libdpi. Unable to load the default library libdpi Can you help us with solving the problem?

Hello Friends, I am new to UVM and very very eager to learn it, I am using windows version of Questasim10.0c, I download the uvm package from accellera. I tried to compile and run code from the the integrated examples - "ubus". 1. Created a project in the below folder "uvm-1.1\examples\integrated\ubus 2. I have added all the files in the folder "uvm-1.1\examples\integrated\ubus\sv" 3. Compiled the files, and facing problems with compilation itself. errors while trying to compile "ubus_master_driver.sv" ** Error: D:/methodologY/UVM/uvm-1.1/examples/integrated/ubus/sv/ubus_master_driver.sv(28): near "uvm_driver": syntax error, unexpected IDENTIFIER ** Error: D:/methodologY/UVM/uvm-1.1/examples/integrated/ubus/sv/ubus_master_driver.sv(28): Error in class extension specification. ** Error: D:/methodologY/UVM/uvm-1.1/examples/integrated/ubus/sv/ubus_master_driver.sv(37): (vlog-2163) Macro `uvm_component_utils_begin is undefined. ** Error: D:/methodologY/UVM/uvm-1.1/examples/integrated/ubus/sv/ubus_master_driver.sv(37): near "(": syntax error, unexpected '(', expecting function or task. Please help me out, i am very eager to learn this language. With Regards MaxImuZ

I tried, for some now, to run a successful simulation in Cygwin using Makefiles. I got to a point where the compilation is without errors, only some warnings like: uvm_sequence.svh(89): (qverilog-2283) Extra semicolon in $unit (global) scope (UVM1.0) My problem comes after that. After the vsim command is issued, no printing appears on the screen and I can't write anything in the window anymore. The Questasim does its job, I can the log files but to run it again I have to close the Cygwin and reopen it. If someone could help it, I would really appreciate it. Thanks!

Cadnece Gentlemen, As a user of both irun and vcs, I think it is a pity that some useful syntax that irun does not support. For example as you could see below attached code, the line which marked "VCS only" in the following uvm_reg related code. I could understand that you do not support regualar expression because LRM seems does not have it. however, I can not find other alternative way for this purpose. (LRM should consider to add this.) For the concatenated function call(). it is also important because it improves the readibilty a lot. I need to write 2 more lines to write the same thing. I hope that someday irun could also support these features. thanks! (now I am using 10.20s15) foreach (regs[i]) begin // Ignore all RST or CK Control registers if ( regs[i].get_name().match(".*[RST|CK]_CTRL.*") ) continue; // VCS only // Write a Random value to the "RW" fields. regs[i].get_fileds(fields); foreach (field[j]) if ( fields[j].get_access().compare("RW") ) // VCS only field[j].set($urandom % (1<<filed[j].get_n_bits())); // Updates to DUT and read back with checks. regs[i].update(st); regs[i].mirror(st, UVM_CHECK); end