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  2. shubham_v

    d flipflop output

    Hi deepti, ok,i got it. Thanks for the help. Regards, Veeresh k
  3. SDeepti

    d flipflop output

    No, you need to have loop with the function registered as SC_THREAD. For your code, it will be: void d_operation() { while(1){ if (reset.read()==1) { d_out = 0; // std::cout << "reset= " << reset << "...din= " << d_in << ".....d_out" << d_out << std::endl; } else { //d_out.write(d_in.read()); d_out=d_in; // wait(1, SC_NS); // std::cout << "reset= " << reset << "...din= " << d_in << ".....d_out" << d_out << std::endl; } wait(); } }
  4. Roman Popov

    Synthetizable FFT function in SystemC

    If you code your FFT as a pure C++ function, Vivado HLS will generate inputs and outputs automatically from function parameters and based on INTERFACE pragmas. And you can import generated RTL into Vivado IP integrator. Check out Xilinx documentation, and ask on Xilinx forums. Please also note that you can implement FFT in a various ways (with different micro-architectures), and achieve various performance vs area numbers. And HLS also requires quite a lot of learning to achieve good results.
  5. Teddy Minz

    Synthetizable FFT function in SystemC

    I didn't use Xilinx's LogiCore because I want to compare the execution time of a VHDL design generated from SystemC-encoded FFT block with the execution time of a FFT block on CPU and precisely with a design who use Xilinx's IP. The objective isn't to have high accuracy but just an order of magnitude between this 3 methods. At the base I didn't want to reinvent the wheel. I thought I could get a SystemC-encoded FFT block and compared it fairly quickly. Excuse me, my questions are maybe silly but I really want to understand. If I code a FFT in pure C++ shall I have problems for testing ? When I code in SystemC I can declare input/output with "sc_in" and "sc_out" and I find them when I import my IP within Vivado. How I can do that in pure C++ ?
  6. shubham_v

    d flipflop output

    Hi deepti, Thanks for your reply. I have tried the other examples also,but tats the commmon issue iam facing of not getting output. By infinite loop, you mean to say i need to put sc_start(-1) which in turn makes my thread to run forever. As far as my problem is concerned,even for combinational circuits if iam using sc_method ,i am not getting the desired output. Update:-Started writing the fresh code and i am getting some ouput now.Some issues are there with respect to timing,but i think it can be resolved. Regards, Shubham
  7. David Black

    Heartbeat, clock and negedge

    No specific guidelines or cookbooks; however, it is really quite straightforward to think about. First, you need to think about contributors to slow down. Some of the worst are: I/O - for example printing out values every time something changes. During debug this may be helpful, but once it's working drop the messaging. Use SC_REPORT_INFO_VERB with appropriate verbosities (e.g. DEBUG). Context switching - every call to wait() implies a context switch. This also applies to returns from SC_METHODs. Second, when you have working code, you need to do code profiling to see where time is being spent. Then think about how to reduce it. Common mistakes: Coding at too low a level of abstraction - NO RTL please Trying to outwit the compiler with "more efficient coding" Using C rather than C++ techniques (e.g. implementing a linked list rather than using appropriate STL containers) Preferring SC_METHOD over SC_THREAD because of the myth that it will be faster (and wasting a lot of coding time doing it) Using sc_clock
  8. David Black

    Synthetizable FFT function in SystemC

    I agree with @Roman Popov on the choice of inputs to the HLS tool. The sweet spot for Vivado_HLS is C++. Much simpler to code for most folks. That said, it can be done. Why wouldn't you want to use Xilinx' Logicore though? One of the best ways of raising the level of abstraction (which is what using C++ or SystemC do) is to reuse somebody else's effort. Tested and probably fairly optimized. Otherwise, you are effectively reinventing the wheel.
  9. SDeepti

    d flipflop output

    You have registered d_operation() as a thread. Ideally a thread should have an infinite loop and a wait(). Adding that, you can see changes to your d_out. Also, how about having another thread that does the reset job?
  10. Roman Popov

    Synthetizable FFT function in SystemC

    Xilinx HLS tools have very limited SystemC support, you should probably code your FFT in pure C++.
  11. David Black

    Triggering a method upon change in value of port

    Show some code. [Use the code quotations <> above and specify language C/C++] What do you mean by "input port"? Are you using the default sc_port or specialized signal port? Have you registered the method? Where are you using value_changed_event()? Why are you using `operator.` rather than operator-> ?
  12. Hi All, I am using an input port of type double to trigger my method. Irrespective of whether I give dont_initialize() property to the method or not, the method is getting triggered once during initialization phase. It is not triggering when there is a change in the value of the port to which the method is sensitive to. I also tried giving .value_changed_event() to the port. How should I handle this? Thanks in advance for your inputs Best Regards, Karthik Rao
  13. Teddy Minz

    Synthetizable FFT function in SystemC

    Thanks for your answer. Sorry for my question maybe evident. Effectively, I begin with SystemC and I am not yet very comfortable with the HLS tools. Nevertheless, is my approach good? I want to say, Is cut the FFT's mathematical formula will allow me to implement it ? Is the simpler way to do this ? The goal is to code a FFT with SystemC and not to use the logicore provided by Xilinx. I've see a fft's library but it need Xilinx's Logicore.
  14. shubham_v

    d flipflop output

    Hi, I have came back to system c after 6 months, again. I was trying to solve different basic examples of system c. The code is getting compiled,but i am not able to view the desired output. My output is not at all changing,i am not sure whether my function is getting hit or not. Please have a look at the code below and any help would b appreciated. In code,i have added stimulus first and then monitor to check wheteher my function was getting invoked.Again ,in main file also i passed the input. But from ,nowhere i am getting the output. Please help! https://www.edaplayground.com/x/5qEA Ps:Not only this example,the other examples such as combinational circuits,encoders,decoders. I am facing the same issue with respect to all of them.There must be a common mistake which i am repeating. Thanks & regards, shubham_v
  15. David Black

    Synthetizable FFT function in SystemC

    You paint a very bleak and incorrect picture of the HLS tool. I will suggest that you need to get some training on its use. Xilinx have many examples and their documentation is quite good. Document UG902 clearly documents the HLS math library which supports all manner of synthesizable operations. For instance: Trigonometric Functions: acos, atan, cospi, acospi, atan2, sin, asin, atan2pi, sincos, asinpi, cos, sinpi, tan, tanpi Hyperbolic Functions: acosh, asinh, cosh, atanh, sinh, tanh Exponential Functions: exp, exp10, exp2, expm1, frexp, idexp, modf Logarithmic Functions: ilogb, log, log10, log1p Power Functions: cbrt, hypot, pow, rsqrt, sqrt Error Functions: erf, erfc Gamma Functions: lgamma, lgamma_r, tgamma Rounding Functions: ceil, floor, llrint, llround, lrint, lround, nearbyint, rint, round, trunc and that's only a few. Perhaps your grasp of C++ and what can or cannot be synthesized is limited. For instance, dynamically allocated memory is forbidden because it is not reasonable to expect silicon to grow new logic during operation. Please read the fine manual (RTFM).
  16. Hmm, I've just run into this bug, Do we know if it's been patched?
  17. Hi everyone, As part of my job I try to implement a FFT function in my ZedBoard. I found some example including one in the SystemC folder unfortunately not synthesizable. Furthermore, I use a free version of Vivado HLS and this tool is very restrictive (few things are synthesizable). So, I will going to have to code my own version of this function (8k/16k/32k FFT). For doing this, I started by cut the FFT's mathematical formula and try to code a exponential function. I realized I can't use the "math.h" library and then I have to code all with only logic gates. At this level, I prefer to code directly in VHDL. Does anyone have a experience with this synthesis tool and can give me a simpler way to achieve my goal ? Maybe I see the problem of the wrong angle. Best regards
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  19. dilawar

    Heartbeat, clock and negedge

    Thank you for this. Are there any list of guidelines you would suggest for improving simulation performance?
  20. dilawar

    Deleting a binding

    Thanks. This is informative hint. cheers, Dilawar
  21. Eyck

    Deleting a binding

    Hi, deleting a binding is not supported. You did not detail your scenario in terms of producer and consumer. Ports in itself are only some kind of a proxy or function-forewarder. So if you have a producer having a sc_out you cannot bind it to some sc_in port of a consumer. You alway have to have a signal in between. Or in terms of C++ a port just forwards function (an interface) but you need to have an element implementing or providing these functions (an implementation). Bottomline: To connect some producer/writer to a consumer/reader thus fowarding a signal write you need to have a signal in between. Best regards
  22. Did anyone try to build extended routing architecture attaching one or more SimpleBusAT from systemc-2.3.3\examples\tlm to another SimpleBusAT ?(from https://www.accellera.org/downloads/standards/systemc) In the examples, SimpleBusAT will route initiator packets to another target. I wonder if SimpleBusAT could be another target and correspondingly route the packets further. Thanks, Dave
  23. dilawar

    Deleting a binding

    Hi, I am dynamically populating a network of SC_MODULES inside a global modele `net`. As soon as I create a module `x`, I bind all ports to x (say `a` and `b`) to `sc_signal` x.a and x.b in `net`. When I simulate, all SC_MODULEs run independently and I can see values of `sc_signal`s changing when port value changes. So far so good! This has the advantage and end-user does not have to bind all the ports (many of them are really not essential). Now I wish to connect port `a` and `b` of module `x` to port of `m` and `n` of module `y`. Any new binding will raise an error since I am allowing maximum of 1 binding. I can change the number of binding to 2 but I am not sure if it will cost me run time penalty. If penalty is not significant I can go with this. Anyway I was wordering, how can delete the previous binding on port `m` and `n`? Deleting the signal `y.m` and `y.n` is sufficient? If it is not possible, I'll think of something else.
  24. dilawar

    Making a port optional

    Thank you maehne. I'll use the `sc_port` solution. It clearly marks my intention in declaration. cheers, Dilawar
  25. maehne

    Making a port optional

    If you don't use the member functions added that were added for convenience to `sc_in`, `sc_out`, and `sc_inout` to, e.g., call `read()`, `write()`, and the event member functions via the `.` operator than via the corresponding member function in the interface accessed via the `->` operator, you might be able to avoid entirely the derivation of new port classes. Instead, you could simply use a template alias, which was introduced with C++'11: template<typename T> using sc_in_opt = sc_core::sc_port<sc_signal_in_if<T>, 1, SC_ZERO_OR_MORE_BOUND>; template<typename T> using sc_inout_opt = sc_core::sc_port<sc_signal_inout_if<T>, 1, SC_ZERO_OR_MORE_BOUND>; template<typename T> using sc_out_opt = sc_core::sc_port<sc_signal_inout_if<T>, 1, SC_ZERO_OR_MORE_BOUND>; If you want to also provide all member functions of `sc_in`, `sc_out`, and `sc_inout`, you will have to derive from the `sc_port` class and implement the full interface as defined in IEEE Std 1666-2011.
  26. dilawar

    Making a port optional

    https://www.doulos.com/knowhow/systemc/new_standard suggests to do the following. sc_port<i_f, 1, SC_ZERO_OR_MORE_BOUND> opt_port; I am trying to replace some of my `sc_out` and `sc_in` with optional ports. I would like to replace them with `sc_out_opt` and `sc_in_opt` class in headers of my modules. What is the best way to derive these classes such that my code-base works with minimal changes to code? 1. Should I derive them from `sc_port<i_f, 1, SC_ZERO_OR_MORE_BOUND>` or `sc_in` and `sc_out` classes? 2. Can I force a port policy on `sc_in` and `sc_out` in module constructor? Any other suggestions?
  27. David Black

    Heartbeat, clock and negedge

    You can use it however you like. We didn't use it everywhere and I'm sure there are more areas where it might be applicable. The main point is that "Performance is a function of simulator CPU activity and how well it used." In some cases such as clocks, there is a lot of activity that goes unused. Many designs really only use the positive edge of the clock. In some designs, the activity can even be reduced significantly. Another instance is timers that often are only touched when they are set up and timeout after N clocks. The RTL approach to modeling a timer decrements the timer value on every clock. A behavioral approach would be: void set_timer( int N ) { assert( N > 0 ); delay = N * clock.period(); setup_time = sc_time_stamp(); projected_time = setup_time + delay; timeout_event.notify( delay ); } The current value of the timer can always be had with: int get_timer_value( void ) { return ( projected_time - sc_time_stamp() ) % clock.period() ); } So you really don't even need the clock in many instances. Instead replace clock.period() with a simple constant. Fast and smart SystemC models don't use sc_clock at all.
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