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  3. Roman Popov

    SC_VECTOR declaration causes Exception thrown.

    Looks like null pointer dereference. I don't immediately see a problem in code samples you provide. Probably bug is somewhere else. Use debugger to identify the root cause of problem.
  4. Used by synthesis tools. Semantically almost identical to: SC_THREAD( my_thread ); sensitive << clock.pos(); Can be used for cycle modeling, but uses a costly sc_clock.
  5. David Black

    sensitivity list

    You can only specify sensitivity on objects that have events or event finders directly accessible at the time of construction. Normally this means using either a suitable channel, port or explicit event. If you wrap your int's with a channel such as sc_signal<T>, you can do it. Example - https://www.edaplayground.com/x/5vLP
  6. TRANG

    sensitivity list

    sensitive<< rd_addr I think above code is illegal. You can declare event. If new value rd_addr != old value rd_addr then notify event .
  7. Mat

    sensitivity list

    I have recently started learning SystemC and I have got an error with sensitivity list in "SC_METHOD". I am trying to implement a fifo and the error corresponds to following part of the code: SC_MODULE(fifo){ ... sc_int<8> rd_addr, wr_addr; ... void buffer_full(); ... SC_CTOR(fifo){ SC_METHOD(buffer_full); sensitive << rd_addr << wr_addr; } }; I get error when compiling the code and it complains about sensitivity list. I would appreciate if someone could let me know what is wrong with the sensitivity list. how should I make "buffer_full" process sensitive to the changes in rd_addr and wr_addr. I also tried following syntax to see if it works with single bit sensitivity but still no success sensitive << rd_addr[0]; Many thanks
  8. Does SystemC SC_CTHREAD( clocked thread) has something to do with cycle accurate modeling? If no, then what is the use of SC_CTHREAD?
  9. Hi , Yes i am getting things slowly.Its all with respect to speed ,accuracy and complexity. Ok eyck,thanks a lot for the answers. Regards, shubham
  10. Insert timing delays with sc_core::wait(sc_time) method as called out by either the specification or your best understanding of the likely RTL result. Perhaps you have a function that compresses a JPEG image and experience shows that it take 550 to 568 clocks on an existing design. If you think you can improve the algorithm by 30% then using some statistical approach: #include <systemc> #include <random> sc_core::sc_time const period { 15.0, SC_NS }; //< clock period ... void compress_jpeg( args... ) { unsigned int seed = 1; std::default_random_engine generator { seed }; std::uniform_distribution<int> distribution { 550, 568 }; // Compress jpeg using software methods ... wait( 0.30 * distribution(generator) * period ); } No magic. Accuracy is dependent on your experience and best effort WAG. You may have a more sophisticated time calculation if you think you know more.
  11. Establish a clock period and insert appropriate wait( N*period ) as needed. Cycle accurate is seldom actually required, and cycle approximate is more likely. For instance, if you know that read transactions on a bus take 2 clocks and you make 5 accesses, you can lump that into a single 2 * 5 * period delay.
  12. Hi i am trying to understand how we can insert timings in an untimed model any example will be a great help thanks khushi
  13. Hi how to develop a cycle accurate model using systemc. any example or pointers will be a great help thanks khushi
  14. Yesterday
  15. Well, in TLM1.0 there is even a tlm::tlm_fifo channel which provides something similar what you use. The sockets defined in TLM2.0 are more geared towards memory-mapped busses and provide facilities to model for speed (DMI, loosly-timed blocking interfaces) or accurracy (approximately-timed non-blocking interfaces). To achive this with pure SystemC provided classes takes some effort and it ends to be proprietary... BR -Eyck
  16. Hey guys, Need help about this: Exception thrown at 0x00007FFC1FCE1CAF (ntdll.dll) in mytest.exe: 0xC0000005: Access violation reading location 0x0000000000000000. I traced the call stack to where it stopped in my code, found it's this line in header file: sc_vector<sc_signal<float>> output_connect_wire{"output_connect_wire",1}; It's been used like this in cpp file, not sure if it's relevant though: .... submodule->O_data(output_connect_wire); .... if(...){...} else { data_out.write(output_conncet_wire[0].read()); } .... where the submodule output declared as sc_vector<sc_out<float>> O_data{"O_data",1}; Thank you in advance and tell me if you need any more info to identify the issue.
  17. Hi eyck, Thank you for the answer. Bu with respect to point 2 of your answer i.e producer ,consumer and fifo example.If i am using read or write operation then its a higher abstraction level and i am aware about it .But where does this concept of initiator ,target and socket comes? Though i am feeling like both are same,but exactly i dont know why should i use them . I had read it that system c and tlm combinedly will be helpful in architecture exploration and performance modelling. Ok ,so acc. to my understanding now, i can relate prod,cons,and fifo to a tlm standard.In tlm , we will be using packet as generic transaction,we are having initiator which will use any of the interface methods like blocking,non blocking and what about the function which we need to implement ?,where will i put that function ? Thanks for the example suggestion, i will look into it. Regards, Shubham
  18. Last week
  19. Teddy Minz

    Synthetizable FFT function in SystemC

    Thanks a lot @Roman Popov !
  20. Roman Popov

    Synthetizable FFT function in SystemC

    From SystemC standard: SystemC requires that you add sc_module_name as a parameter to module constructors, like this: MULT(sc_module_name, int var_a, int var_b); MULT(sc_module_name); This is a hack that allows SystemC kernel to track lifetime of constructor.
  21. Hi, TLM2.0 is used to model bus-like transactions as you have in APB, AHB, AXI or alike. It abstracts those transactions in to e.g. read and write with some attribites (liek protection and alike). This saves some from dealing with bit wiggling and, as you have less events, improves simulation performance. If you use in your scenarion fifo between your producer and consumer you are already using TLM as you abstract the transmission of more or less complex data as a write into the fifo. If you keep this style in your design you do transaction level modeling (TLM). If you are asking if it makes sense to use the TLM2.0 standard is a different question and depends on what aspects of your design do you need to represent in your model. If you have some kind bus structure (e.g. some micro processor or controller) then it is highly advisable to use TLM2.0. In that case your producer calls the transfer functions of the initiator socket and your consumer needs to react on the callbacks of the target socket. Actually this does not relate to your file structure but as a starting poitn I would suggest to study the lt example comign with the SysetmC distribution. You will find it under examples/tlm/lt, it contains 2 initiator_top mdouels, a bus and 2 lt_target modules. if you reduce the thing to just one initiator_top and one lt_target being directly connected you have your producer/consumer scenario. HTH
  22. Teddy Minz

    Synthetizable FFT function in SystemC

    Hi everyone, Thanks to you, I was able to advance. I have follow your advice and I succeeded to synthesize a FFT function in pure C++ with Vivado HLS. Now, I would like to insert this function in a structure SystemC. For do this I have create a little project "multiplication" . But I think I have difficulties to understand the "SC_CTOR"... I have try to create standard constructor like in C++ but SystemC don't like my constructor ^^ module.cpp #include "module.h" using namespace std; void MULT::multiplication(void) { result = A * B; } void MULT::afficherResult() const { cout << A << " * " << B << " = " << result << endl; } MULT::MULT() : A(4), B(5), result(0) {} MULT::MULT(int var_a, int var_b) : A(var_a), B(var_b), result(0) {} module.h #include "systemc.h" #include <iostream> SC_MODULE(MULT) { public: // Constructeur MULT(int var_a, int var_b); MULT(); //SC_CTOR(MULT); void multiplication(void); void afficherResult() const; private: int A, B, result; }; main.cpp #include "module.h" int sc_main(int argc, char* argv[]) { MULT mult1; mult1.multiplication(); // Print result mult1.afficherResult(); return 0; } With this code I have the following error : Error: (E533) module name stack is empty: did you forget to add a sc_module_name parameter to your module constructor? Why this code work if I declare a classic C++ class but it doesn't with a SC_MODULE? With SystemC we cannot create constructor like that ? Best regards
  23. To be clear: I cannot use `uvm_blocking_transport_imp_decl(SFX) macros, because I need to use TLM2 sockets at the UVM-SV side.
  24. Thanks David, but I already know about the SystemC side 🙂 I'm looking for possibilities in the UVM-SV space (hence the post in "UVM SystemVerilog Discussions").
  25. Hi, I was having few basic doubts regarding tlm,I am using system c again after few months. I wanted to know ,how exactly tlm is being used.I know the basics of system c and was approaching to start with tlm. I had googled to see few of tlm uses,but i was not able to catch up those points. I want to know under this scenario,like if i had modelled a system in system c and was having 5 files,design.cpp,producer.cpp,consumer.cpp,top.cpp,main.cpp .I would have used threads as function and called at particular time and would do the communicvation between modules.But what about tlm,as i had read in tlm we are having initiator and target and there are different types of interface connections which can be used for communication. But my question here would be,how and where would i put those 5 files when commuication mode being used is tlm.Do i need to model producer as initiator & vice versa & use any of the interface method of tlm or what !? Any help would be appreciated a lot. Thank you. Regards, Shubham
  26. By using convenience sockets, you can bind each socket to a different function (names will have to be different because the argument types are the same). Thus, twotarg.hpp: // Example code with two target sockets and separate implementations #ifndef TWOTARG_MODULE_HPP #define TWOTARG_MODULE_HPP #ifndef SC_INCLUDE_DYNAMIC_PROCESSES #define SC_INCLUDE_DYNAMIC_PROCESSES #endif #include <tlm> #include <tlm_utils/simple_target_socket.h> #include <cstdint> // Specific symbols for convenience using sc_core::sc_time; using sc_core::sc_event; struct Twotarg_module: sc_core::sc_module { // Type definitions to improve readability using tlm_payload_t = tlm::tlm_generic_payload; using tlm_phase_t = tlm::tlm_phase; using tlm_peq_t = tlm_utils::peq_with_cb_and_phase<Twotarg_module>; // Sockets, ports and exports tlm_utils::simple_target_socket<Twotarg_module> targ_socket_2{ "targ_socket_1" }; tlm_utils::simple_target_socket<Twotarg_module> targ_socket_2{ "targ_socket_2" }; Twotarg_module ///< Constructor ( sc_core::sc_module_name instance_name ); ~Twotarg_module( void ); ///< Destructor (allow PIMPL) virtual const char* kind( void ) const override { return "Twotarg_module"; } private: //---------------------------------------------------------------------------- // Forward interface void b_transport_1( tlm_payload_t& trans, sc_time& offset ); void b_transport_2( tlm_payload_t& trans, sc_time& offset ); private: Twotarg_module( const Twotarg_module& ) = delete; Twotarg_module& operator=( const Twotarg_module& ) = delete; }; #endif /*TWOTARG_MODULE_HPP*/ and twotarg.cpp: //File: twotarg.cpp #include "twotarg.hpp" namespace { const char* const MSGID{"/Doulos Inc./Example/Twotarg"}; } using namespace sc_core; using namespace tlm; using namespace std; //------------------------------------------------------------------------------ Twotarg_module::Twotarg_module // Constructor ( sc_module_name instance_name ) { targ_socket_1.register_b_transport ( this, &Twotarg_module::b_transport_1 ); targ_socket_2.register_b_transport ( this, &Twotarg_module::b_transport_2 ); } //------------------------------------------------------------------------------ // Destructor Twotarg_module::~Twotarg_module( void ) { } //////////////////////////////////////////////////////////////////////////////// // Forward interface //------------------------------------------------------------------------------ void Twotarg_module::b_transport_1 ( tlm_payload_t& trans , sc_time& delay ) { SC_REPORT_INFO_VERB( MSGID, "Not yet implemented", SC_NONE ); ///< replace this line // TO BE SUPPLIED // Check attributes // Perform transaction } //------------------------------------------------------------------------------ void Twotarg_module::b_transport_2 ( tlm_payload_t& trans , sc_time& delay ) { SC_REPORT_INFO_VERB( MSGID, "Not yet implemented", SC_NONE ); ///< replace this line // TO BE SUPPLIED // Check attributes // Perform transaction } /////////////////////////////////////////////////////////////////////////////// // Copyright 2019 by Doulos Inc.. All rights reserved. //END twotarg.cpp
  27. In SystemC, we have the possibility to bind a specific b_transport function to a specific target socket. Hence, I can create a module with multiple target sockets that each bind to their own b_transport implementation. Reading the UVM user's guide v1.2 chapter 2.47 (TLM2 - Use Models), I get the impression that there exists an implicit binding between all target sockets of a module and one b_transport implementation. In other words, we can only have one b_transport function per uvm_component. Is that correct, or is there a way to implement and bind different b_transport implementations to different target sockets?
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