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  1. Today
  2. All of these relate to the concept of loosly-timed simulation. The basic principle behind this is that parts of the design can simulate larger time slices without returning control to the simulation kernel; the run ahead of the rest of the simulation. This is used e.g. for processors and alike as for quite some parts the do not interact with the rest of the design and create (a memory read does not really trigger any action other than returning some data). This way the simulation speed and hence the simulation performance can be drasticalliy improved but you trade performance for accuracy. This domain (or part of the simulation) running ahead of the simulation kernel is temporally decoupled. As such it needs some mechanism to control its local time (the amount it is ahead of the simulation kernel). This is done by the quantum keeper, the quantum is the amount of time the decoupled domain is allowd to be ahead at max. To allow interaction with the rest of the design all interaction need to carry some information what the local time in the dcoupled domain is, this is called timing annotation. This information is needed to either schedule events in the simulation kernel to happen at the correct time or to decide to break the quantum which means the decoupled domain is stopped and control is returned to the simulation kern until it reaches the local time of the decoupled domain, they are in sync then. HTH
  3. Hi all, Can you explain about ideas of "Timing annotation", "Temporal decoupling", "Quantum keeper"? How do you use it?.
  4. Yesterday
  5. Probably you talk about cycle-based simulators? Like for example Verilator (https://www.veripool.org/wiki/verilator). Cycle-based simulators are faster than discrete-event simulators if you have a cycle-accurate model like RTL. Also cycle-based simulation is easier to parallelize. Oftern pin-level interfaces are used to integrate some RTL into C++ simulators. Or opposite, integrate high-level C++ simulators into RTL verification environment. Commercial simulators like VCS can automatically generate SystemC pin-level wrapper for Verilog, or Verilog wrapper for SystemC. Then you can do cosimulation. Another usage for pin-level interfaces is High-Level Synthesis. HLS tools from Cadence and Mentor take SystemC models with pin-level interfaces as an input.
  6. Last week
  7. Thanks David I have few connected questions There are lot of people talk about cycle accurate models to speed up the simulation. What are those cycle accurate models? Are those written in SystemC ? If not can you explain a bit on this. Can we connect an untimed tlm model to a rtl block and simulate it seamlessly. Do we need to take care few things in untimed tlm model to make it work in a cosimu environment? I remember someone implementing a SystemC model with individual axi pins as sc_bv/sc_lv types instead of using the tlm2 socket. What are the usage of such models? Suppose I connect a tlm2 socket to a rtl axi interface using some adapter eg tlm2axi, in this case do we need cycle accurate or approximate model on tlm side for a smooth operation. Thank khushi
  8. Well, to me it is always helpful to think about sockets as a proxy or sophisticated function forwarder (in some sense similar lto sc_port). So you call b_transport on the initiator side and the socket forwards the call to the target and invokes b_transport there. HTH
  9. At first glance, you can call b_transport from C++, but it must be C++ that is inside a SystemC process during simulation phase if the b_transport call invokes sc_core::wait(). You can read the details in the IEEE-1666-2011 specification. Or perhaps you should signup for the Doulos SystemC TLM-2.0 course and get expert hands-on training. Fundamentally, b_transport is a simple function call; however, it may use SystemC semantics to accomplish its work. Hence you should also be knowledgable on SystemC SC_THREADs (may not be used in SC_METHODs). Technically, you could write a b_transport method in the target that did not call sc_core::wait, which is desirable anyhow. If you did this, then you may call from pretty much anywhere; however, SystemC is not thread-safe without special precautions. In any event, there is a lot to learn about the subtleties of the generic payload and extensions too.
  10. Hi, I assume its a basic question . Can someone please help me understand the basic flow of initiator and target by using a blocking interface in a c++ way. I had read the tutorial on doulous ,but i dint get the required explnation from my side. I do know the concepts of c++,but implementation wise i am bit on the slower side. It would be great if someone could explain it here through step wise. Thanks in advance. Ps: just for reference i am putting up the code.initiator.h,target.h,top.h,main.cpp Regards, Shubham
  11. Roman Popov

    SC_VECTOR declaration causes Exception thrown.

    Looks like null pointer dereference. I don't immediately see a problem in code samples you provide. Probably bug is somewhere else. Use debugger to identify the root cause of problem.
  12. Used by synthesis tools. Semantically almost identical to: SC_THREAD( my_thread ); sensitive << clock.pos(); Can be used for cycle modeling, but uses a costly sc_clock.
  13. David Black

    sensitivity list

    You can only specify sensitivity on objects that have events or event finders directly accessible at the time of construction. Normally this means using either a suitable channel, port or explicit event. If you wrap your int's with a channel such as sc_signal<T>, you can do it. Example - https://www.edaplayground.com/x/5vLP
  14. TRANG

    sensitivity list

    sensitive<< rd_addr I think above code is illegal. You can declare event. If new value rd_addr != old value rd_addr then notify event .
  15. Mat

    sensitivity list

    I have recently started learning SystemC and I have got an error with sensitivity list in "SC_METHOD". I am trying to implement a fifo and the error corresponds to following part of the code: SC_MODULE(fifo){ ... sc_int<8> rd_addr, wr_addr; ... void buffer_full(); ... SC_CTOR(fifo){ SC_METHOD(buffer_full); sensitive << rd_addr << wr_addr; } }; I get error when compiling the code and it complains about sensitivity list. I would appreciate if someone could let me know what is wrong with the sensitivity list. how should I make "buffer_full" process sensitive to the changes in rd_addr and wr_addr. I also tried following syntax to see if it works with single bit sensitivity but still no success sensitive << rd_addr[0]; Many thanks
  16. Does SystemC SC_CTHREAD( clocked thread) has something to do with cycle accurate modeling? If no, then what is the use of SC_CTHREAD?
  17. Hi , Yes i am getting things slowly.Its all with respect to speed ,accuracy and complexity. Ok eyck,thanks a lot for the answers. Regards, shubham
  18. Insert timing delays with sc_core::wait(sc_time) method as called out by either the specification or your best understanding of the likely RTL result. Perhaps you have a function that compresses a JPEG image and experience shows that it take 550 to 568 clocks on an existing design. If you think you can improve the algorithm by 30% then using some statistical approach: #include <systemc> #include <random> sc_core::sc_time const period { 15.0, SC_NS }; //< clock period ... void compress_jpeg( args... ) { unsigned int seed = 1; std::default_random_engine generator { seed }; std::uniform_distribution<int> distribution { 550, 568 }; // Compress jpeg using software methods ... wait( 0.30 * distribution(generator) * period ); } No magic. Accuracy is dependent on your experience and best effort WAG. You may have a more sophisticated time calculation if you think you know more.
  19. Establish a clock period and insert appropriate wait( N*period ) as needed. Cycle accurate is seldom actually required, and cycle approximate is more likely. For instance, if you know that read transactions on a bus take 2 clocks and you make 5 accesses, you can lump that into a single 2 * 5 * period delay.
  20. Hi i am trying to understand how we can insert timings in an untimed model any example will be a great help thanks khushi
  21. Hi how to develop a cycle accurate model using systemc. any example or pointers will be a great help thanks khushi
  22. Well, in TLM1.0 there is even a tlm::tlm_fifo channel which provides something similar what you use. The sockets defined in TLM2.0 are more geared towards memory-mapped busses and provide facilities to model for speed (DMI, loosly-timed blocking interfaces) or accurracy (approximately-timed non-blocking interfaces). To achive this with pure SystemC provided classes takes some effort and it ends to be proprietary... BR -Eyck
  23. Hey guys, Need help about this: Exception thrown at 0x00007FFC1FCE1CAF (ntdll.dll) in mytest.exe: 0xC0000005: Access violation reading location 0x0000000000000000. I traced the call stack to where it stopped in my code, found it's this line in header file: sc_vector<sc_signal<float>> output_connect_wire{"output_connect_wire",1}; It's been used like this in cpp file, not sure if it's relevant though: .... submodule->O_data(output_connect_wire); .... if(...){...} else { data_out.write(output_conncet_wire[0].read()); } .... where the submodule output declared as sc_vector<sc_out<float>> O_data{"O_data",1}; Thank you in advance and tell me if you need any more info to identify the issue.
  24. Hi eyck, Thank you for the answer. Bu with respect to point 2 of your answer i.e producer ,consumer and fifo example.If i am using read or write operation then its a higher abstraction level and i am aware about it .But where does this concept of initiator ,target and socket comes? Though i am feeling like both are same,but exactly i dont know why should i use them . I had read it that system c and tlm combinedly will be helpful in architecture exploration and performance modelling. Ok ,so acc. to my understanding now, i can relate prod,cons,and fifo to a tlm standard.In tlm , we will be using packet as generic transaction,we are having initiator which will use any of the interface methods like blocking,non blocking and what about the function which we need to implement ?,where will i put that function ? Thanks for the example suggestion, i will look into it. Regards, Shubham
  25. Teddy Minz

    Synthetizable FFT function in SystemC

    Thanks a lot @Roman Popov !
  26. Roman Popov

    Synthetizable FFT function in SystemC

    From SystemC standard: SystemC requires that you add sc_module_name as a parameter to module constructors, like this: MULT(sc_module_name, int var_a, int var_b); MULT(sc_module_name); This is a hack that allows SystemC kernel to track lifetime of constructor.
  27. Hi, TLM2.0 is used to model bus-like transactions as you have in APB, AHB, AXI or alike. It abstracts those transactions in to e.g. read and write with some attribites (liek protection and alike). This saves some from dealing with bit wiggling and, as you have less events, improves simulation performance. If you use in your scenarion fifo between your producer and consumer you are already using TLM as you abstract the transmission of more or less complex data as a write into the fifo. If you keep this style in your design you do transaction level modeling (TLM). If you are asking if it makes sense to use the TLM2.0 standard is a different question and depends on what aspects of your design do you need to represent in your model. If you have some kind bus structure (e.g. some micro processor or controller) then it is highly advisable to use TLM2.0. In that case your producer calls the transfer functions of the initiator socket and your consumer needs to react on the callbacks of the target socket. Actually this does not relate to your file structure but as a starting poitn I would suggest to study the lt example comign with the SysetmC distribution. You will find it under examples/tlm/lt, it contains 2 initiator_top mdouels, a bus and 2 lt_target modules. if you reduce the thing to just one initiator_top and one lt_target being directly connected you have your producer/consumer scenario. HTH
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