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UVM 2017 - Methodology and BCL Forum

Use this forum for posting questions about the 2017 UVM library and its application to verification environments.

12 topics in this forum

  1. What's New in IEEE-UVM?

    By bhunter1972,   
    • 1 reply
    • 568 views

  2. Purpose of uvm_reg_map::backdoor() and Related Warning with Backdoor Write of UVM_MEM

    By markeduda,   
    • 1 reply
    • 501 views

  3. UVM phase jumping to extract phase

    By sharvil111,   
    • 2 replies
    • 449 views

  4. New Library Version Number?

    By jrefice,
    • 0 replies
    • 384 views

  5. New UVM Reference Implementation Now Available

    By Lynn Garibaldi,
    • 0 replies
    • 334 views

  6. drive same sequence to multiple driver

    By Khushi,
    • 3 replies
    • 283 views

  7. Function do_compare override in uvm_sequence_item derived class - compare always returns '1'

    By Rolko,   
    • 1 reply
    • 270 views

  8. UVM Library Test Suite and Git Repository

    By sas73,
    • 3 replies
    • 218 views

  9. Possible bug in UVM IEEE

    By DarkFeri,   
    • 0 replies
    • 216 views

  10. Access synchronization issue in uvm_reg class observed

    By thorsten69,   
    • 3 replies
    • 108 views

  11. UVM Based Verification Of Modern Microprocessors

    By Krishna Kumar,   
    • 0 replies
    • 98 views

  12. Possible bug in uvm_create_random_seed()

    By jeff.schroeder,
    • 1 reply
    • 79 views
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