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UVM SystemVerilog Discussions

Use this forum when your question is about SystemVerilog language issues in the context of UVM. These can be about how to use a language feature is user code with the UVM or about language usage inside the UVM BCL.

596 topics in this forum

  1. uvm_reg_field.get_access() method returns wrong value

    By Petr Kobiersky,
    • 1 reply
    • 1.2k views

  2. how to unpack payload?

    By swapnilm,
    • 12 replies
    • 17.1k views

  3. AHB , bus2reg , reg2bus in hrdata & hwdata

    By soleshka,
    • 1 reply
    • 1.7k views

  4. UVM RAL implementation methodology for large designs

    By rgarciaf071,   
    • 1 reply
    • 1.8k views

  5. Unresolved reference to 'create_item' in $root.create_item !!!!

    By qinhailiang,
    • 2 replies
    • 4.9k views

  6. How can I print out Logs left-aligned?

    By karlzhao,
    • 2 replies
    • 5.4k views

  7. Possible bug: UVM 1.2,IEEE: uvm_transaction.svh, etc.

    By kaushalmodi,   
    • 2 replies
    • 2.6k views

  8. Volatile bit set for RO registers

    By Narendra,
    • 0 replies
    • 1.6k views

  9. monitor output is delayed due to run_phase ordering

    By Khushi,
    • 1 reply
    • 1.7k views

  10. Do we need to use two monitors one each for input and output

    By Khushi,
    • 1 reply
    • 1.5k views

  11. UVM phase jumping to extract phase

    By sharvil111,   
    • 1 reply
    • 5.8k views

  12. Cause of UVM Timeout

    By sas73,
    • 3 replies
    • 4.8k views

  13. drive same sequence to multiple driver

    By Khushi,
    • 2 replies
    • 1.3k views

  14. unsuccessful factory override

    By ori,
    • 2 replies
    • 1.1k views

  15. Alternate Scoreboarding approach

    By svuvmuser,   
    • 1 reply
    • 1.5k views

  16. End of test in UVM-1.2

    By asic_bg,
    • 0 replies
    • 2.4k views

  17. Behavior of uvm_sequence_base::kill method

    By Taichi Ishitani,
    • 0 replies
    • 957 views

  18. Returning event from virtual function

    By DanaL,
    • 1 reply
    • 1.5k views

  19. Property in assertion

    By venkatasubbarao_Sutrave,
    • 1 reply
    • 2.1k views

  20. Individual uvm_reg_field exclusion from uvm_reg_hw_reset_seq possible?

    By obajaj,
    • 1 reply
    • 1.3k views

  21. uvm_reg_bit_bash_seq

    By Suguna R,
    • 1 reply
    • 1.5k views

  22. Transaction Design Patterns

    By sas73,
    • 17 replies
    • 3.5k views

  23. Constrained Random Performance

    By sas73,
    • 4 replies
    • 3.2k views

  24. Functional coverage- VCS

    By vaibhav0901,
    • 3 replies
    • 7.1k views

  25. apb_master (in UVM examples) read task is having an issue

    By amg19,
    • 0 replies
    • 1.4k views
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