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UVM SystemVerilog Discussions

Use this forum when your question is about SystemVerilog language issues in the context of UVM. These can be about how to use a language feature is user code with the UVM or about language usage inside the UVM BCL.

596 topics in this forum

  1. null value when trying to get register from top reg map by get_reg_by_offset

    By Ai_Ar,   
    • 0 replies
    • 1.2k views

  2. How to access the instance ID of a class from a base_class, whose child class is instantiated inside.

    By Sujitha,
    • 0 replies
    • 415 views

  3. How do I get multiple transactions if register width is wider or narrower than bus width?

    By qurax,   
    • 0 replies
    • 1.1k views

  4. UVM randomise specific extended class only not other classes

    By Ahmad Fahad,
    • 1 reply
    • 418 views

  5. Multiple target sockets with multiple b_transport functions in one class?

    By Bas Arts,
    • 6 replies
    • 1.5k views

  6. any restrictions on expression in wait(expression)?

    By mastrick,
    • 6 replies
    • 11k views

  7. The question on reactive slave

    By VVdemajia,   
    • 5 replies
    • 2.6k views

  8. What happen if read access is performed on write-only register?

    By meah,
    • 1 reply
    • 2.3k views

  9. Hierarchical names in constant expression

    By Thomas Kruse,
    • 1 reply
    • 2.5k views

  10. Transaction timer expired (WDT)

    By Yan,
    • 5 replies
    • 1.4k views

  11. Printer

    By bl4ckp3rl,
    • 1 reply
    • 499 views

  12. SystemVerilog Assertions not getting included

    By Ankit Shah,
    • 2 replies
    • 556 views

  13. queue/array randomize

    By shanghai1943,   
    • 3 replies
    • 1.4k views

  14. uvm_resource_db confusion

    By shanghai1943,   
    • 2 replies
    • 1.4k views

  15. field.mirror() task not working as expected

    By shreyasraju,   
    • 7 replies
    • 5.1k views

  16. Reduction operator in case of one-bit vector

    By Thomas Kruse,
    • 2 replies
    • 820 views

  17. Array of SystemVerilog Interface

    By Thomas Kruse,
    • 2 replies
    • 3.5k views

  18. time slot vs. time step (1800.1-2017.pdf)

    By ljepson74,   
    • 4 replies
    • 3k views

  19. UVM EVENT or SV issue ?? Strange thread issue....Try if you want to see magic

    By AK_K,
    • 1 reply
    • 1.1k views

  20. reg.randomize doesn't work for some regs

    By Weicai,
    • 0 replies
    • 1.2k views

  21. Could not find call of check_config_usage in UVM library

    By supal,
    • 2 replies
    • 926 views

  22. Learning System Verilog from scratch

    By Dexy10,
    • 1 reply
    • 655 views

  23. Verilog/SystemVerilog Configuration default liblist question

    By cliffc,   
    • 2 replies
    • 2.2k views

  24. Verilog bug issue

    By Tarzan,
    • 2 replies
    • 541 views

  25. How to access register file array data using bind module

    By Dina Emadeldin,
    • 1 reply
    • 1.2k views
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