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UVM SystemVerilog Discussions

Use this forum when your question is about SystemVerilog language issues in the context of UVM. These can be about how to use a language feature is user code with the UVM or about language usage inside the UVM BCL.

596 topics in this forum

  1. assigning queue values from sequence

    By kaggala,   
    • 7 replies
    • 8.4k views

  2. Cross coverage of two covergroups

    By karandeep963,   
    • 7 replies
    • 18.4k views

  3. how to display UVM_VERBOSITY

    By ljepson74,   
    • 2 replies
    • 2.5k views

  4. SV UVM environment, not moving beyond 0 time

    By traj,
    • 2 replies
    • 1.7k views

  5. bus monitoring : Using SVA to pass transactions to monitor?

    By c4brian,
    • 7 replies
    • 2.7k views

  6. uvm_sequence_base kill on virtual sequence

    By ljepson74,   
    • 1 reply
    • 2.7k views

  7. Bug in SV LRM

    By apfitch,
    • 0 replies
    • 1.2k views

  8. member reference resolution error related to uvm_analysis_imp_decl

    By praneeth,   
    • 2 replies
    • 4.6k views

  9. uvm_resource_db usage

    By xua,   
    • 1 reply
    • 2.7k views

  10. SC_FIXED and UVM ML Packer

    By matteodc,
    • 2 replies
    • 1.4k views

  11. Parameterized interfaces

    By antwens,   
    • 4 replies
    • 3.7k views

  12. iff usage (as a mechanism for waiting)

    By ljepson74,   
    • 3 replies
    • 21.2k views

  13. how to use uvm reg callback to implement reg_a read being qualified by a field in reg_b

    By commandos,
    • 3 replies
    • 3.7k views

  14. uvm object into uvm sequence

    By laura,
    • 2 replies
    • 1.6k views

  15. about uvm_reg::add_hdl_path_slice,can I assign a hdl varible declared as "wire""

    By commandos,   
    • 2 replies
    • 5.6k views

  16. execution region of UVM TB

    By rahulkumarkhokher,   
    • 2 replies
    • 1.6k views

  17. Factory override(set_type_override_by_type, set_inst_override_by_type)

    By rahulkumarkhokher,   
    • 1 reply
    • 5.4k views

  18. Phases in uvm

    By rahulkumarkhokher,   
    • 0 replies
    • 1.2k views

  19. uvm_config_db/uvm_resource_db

    By rahulkumarkhokher,   
    • 0 replies
    • 1.1k views

  20. Different packet types with single sequencer.?

    By Balakasaiah,
    • 7 replies
    • 2.3k views

  21. uvm sequence

    By Diva34,   
    • 5 replies
    • 3.6k views

  22. Package in SystemVerilog

    By bhimgudur,
    • 2 replies
    • 2.8k views

  23. `uvm_*_utils macros useful in virtual class extended from uvm_object?

    By ljepson74,   
    • 3 replies
    • 5.1k views

  24. CodingStyle: handle name vs create's string name. To match or not?

    By ljepson74,   
    • 3 replies
    • 3k views

  25. Get verbosity from a module

    By mrussell98,
    • 2 replies
    • 5.3k views
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