UVM SystemVerilog Discussions

596 topics in this forum

1. std::randomize( vs. randomize( vs. this.randomize( and scope

   By ljepson74, May 9, 2013   

   • randomize
   • std::randomize
   • (and 2 more)

     Tagged with:

     • randomize
     • std::randomize
     • scope
     • porridge
   • 3 replies
   • 51.2k views
   • 
   • ajeetha
   • August 18, 2013

2. randomize() with inside syntax

   By ljepson74, April 4, 2016   

   • randomize() with
   • randomize()
   • (and 1 more)

     Tagged with:

     • randomize() with
     • randomize()
     • inside
   • 4 replies
   • 49k views
   • 
   • ljepson74
   • August 21, 2020

3. How to pass variable sized packed arguments to a task/function?

   By farhad01, April 18, 2013   

   • array
   • packed
   • (and 3 more)

     Tagged with:

     • array
     • packed
     • size
     • task
     • function
   • 5 replies
   • 41.3k views
   • 
   • farhad01
   • April 21, 2013

4. how to access verilog module internal signals in UVM testbench

   By mjet08, October 13, 2014
   • 6 replies
   • 39.9k views
   • 
   • c4brian
   • September 21, 2015

5. good technique to generate a random delay?

   By c4brian, October 15, 2015
   • 11 replies
   • 27.7k views
   • 
   • David Black
   • June 4, 2022

6. problem about variable part select in SystemVerilog

   By mrforever, April 18, 2013   

   • variable part select
   • 1 reply
   • 24.1k views
   • 
   • zcahana
   • April 18, 2013

7. simple override example - with error

   By ljepson74, December 4, 2013   

   • override
   • set_type_override
   • 6 replies
   • 22.7k views
   • 
   • ljepson74
   • January 4, 2014

8. iff usage (as a mechanism for waiting)

   By ljepson74, June 5, 2015   

   • iff
   • wait
   • 3 replies
   • 21.2k views
   • 
   • ljepson74
   • June 5, 2015

9. walk thru an enumeration

   By ljepson74, January 23, 2016   

   • enum
   • enumeration
   • (and 2 more)

     Tagged with:

     • enum
     • enumeration
     • .next
     • .first
   • 1 reply
   • 20.8k views
   • 
   • dave_59
   • January 23, 2016

10. fixed-size arrays : Do they not 'support' size()?

    By ljepson74, April 17, 2014   

    • size()
    • array
    • (and 5 more)

      Tagged with:

      • size()
      • array
      • fixed size array
      • fixed-size array
      • built in method name
      • $size
      • irun
    • 3 replies
    • 18.5k views
    • 
    • ljepson74
    • May 2, 2014

11. Cross coverage of two covergroups

    By karandeep963, April 3, 2014   

    • Cross coverage
    • 7 replies
    • 18.4k views
    • 
    • albert
    • August 19, 2015

12. A way of shortening uvm_info filename to ONLY filename, not path/filename?

    By aquarioz, March 27, 2013   

    • UVM_REPORT_DISABLE_FILE_LINE
    • uvm_info
    • 8 replies
    • 17.9k views
    • 
    • halfrater
    • March 17, 2016

13. creating parameterized class (virtual interface) using factory

    By adhingra, February 1, 2013
    • 6 replies
    • 17.4k views
    • 
    • shalsays
    • February 15, 2013

14. how to unpack payload?

    By swapnilm, April 2, 2013
    • 12 replies
    • 17.1k views
    • 
    • milin parekh
    • November 14, 2019

15. UVM_FATAL Errors

    By Hash, January 22, 2013
    • 10 replies
    • 17k views
    • 
    • bcassell
    • November 9, 2023

16. `uvm_do(), `uvm_create/`uvm_send vs sart_item/finish_item

    By Somasekhar, November 15, 2018   

    • uvm_sequence
    • start_item
    • 1 reply
    • 16.8k views
    • 
    • Bhagwan Jha
    • November 30, 2018

17. Displaying only UVM_LOW and UVM_HIGH log infos

    By omahesh, December 27, 2012
    • 2 replies
    • 16.7k views
    • 
    • omahesh
    • January 3, 2013

18. How to write a good Makefile in VCS for running UVM tests?

    By liya, March 11, 2014   

    • UVM
    • 2 replies
    • 16.6k views
    • 
    • David Black
    • April 10, 2014

19. set_global_timeout

    By uvm_rookie, February 7, 2012
    • 8 replies
    • 16.1k views
    • 
    • krb
    • April 5, 2012

20. Difference between uvm_hdl_force and uvm_hdl_deposit

    By shreyasraju, February 27, 2014   

    • UVM
    • Force
    • (and 2 more)

      Tagged with:

      • UVM
      • Force
      • System Verilog
      • Deposit
    • 2 replies
    • 16.1k views
    • 
    • David Black
    • February 27, 2014

21. Can we perform UVM_REG read/write access based on Address?

    By balasubramanian.g@pmcs.com, August 14, 2014   

    • UVM_REG
    • UVM
    • (and 2 more)

      Tagged with:

      • UVM_REG
      • UVM
      • READ
      • WRITE
    • 3 replies
    • 15.3k views
    • 
    • balasubramanian.g@pmcs.com
    • August 19, 2014

22. string literal spanning a newline (using a backslash) - vendor supported?

    By ljepson74, September 28, 2016   

    • string literal
    • backslash
    • (and 2 more)

      Tagged with:

      • string literal
      • backslash
      • newline
      • slash
    • 11 replies
    • 15k views
    • 
    • joniale
    • July 19, 2018

23. Use of intersection in cross coverpoints

    By imajeeth, April 21, 2016   

    • coverage
    • 2 replies
    • 14.2k views
    • 
    • dave_59
    • April 23, 2016

24. How to use a variable defined in one class into another class?

    By swapnilm, April 8, 2013
    • 7 replies
    • 14.1k views
    • 
    • Yuri
    • July 26, 2021

25. How to get virtual interface in sequence

    By praneeth, June 26, 2015   

    • virtual interface in sequenc
    • 7 replies
    • 14.1k views
    • 
    • c4brian
    • August 3, 2016