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UVM SystemVerilog Discussions

Use this forum when your question is about SystemVerilog language issues in the context of UVM. These can be about how to use a language feature is user code with the UVM or about language usage inside the UVM BCL.

596 topics in this forum

  1. `uvm_*_utils macros useful in virtual class extended from uvm_object?

    By ljepson74,   
    • 3 replies
    • 5.1k views

  2. `uvm_do(), `uvm_create/`uvm_send vs sart_item/finish_item

    By Somasekhar,   
    • 1 reply
    • 16.8k views

  3. `uvm_unpack_arrayN Macro

    By jwagner,
    • 0 replies
    • 1.5k views

  4. , help me !!!!!

    By preda,
    • 2 replies
    • 3.7k views

  5. 'run' phase is ready to proceed to the 'extract' phase

    By diju.ms,   
    • 0 replies
    • 3.6k views

  6. 'starting phase' - intended usage

    By ljepson74,   
    • 1 reply
    • 2.9k views

  7. "Mixin" classes - parametrizing the base class

    By alangloria,
    • 11 replies
    • 7.5k views

  8. "uvm sequence library" vs "virtual sequence"

    By Nadun,   
    • 1 reply
    • 1.2k views

  9. “dist”. Can a value_range be a list in a randomization distribution?

    By ljepson74,   
    • 0 replies
    • 1.6k views

  10. [RAL] Dealing with 64b/32b register write/read with same reg_model

    By ASRAJARAJAN,
    • 1 reply
    • 2.5k views

  11. [REG_PREDICT_COLLISION] Collision detected for register ...

    By Ryan100,
    • 1 reply
    • 2.1k views

  12. [System verilog ] Accessing an array with range varying along with upper and lower limits and the width of the array .

    By rajivdesh,   
    • 2 replies
    • 1.8k views

  13. [virtual interface] Is is possible to pass one signal by task argument ?

    By light12,
    • 3 replies
    • 7k views

  14. ** Error: Failed to find name '__m_uvm_status_container' in specified scope

    By sharmadiksha,
    • 2 replies
    • 2.9k views

  15. $system() function return value OR Setting a random sim seed within SystemVerilog code using wallclock time.

    By ljepson74,   
    • 8 replies
    • 4.3k views

  16. 3 TLMs between sequencer and driver?

    By swapnilm,
    • 2 replies
    • 1.9k views

  17. 8b10b function

    By rlanier,
    • 0 replies
    • 1.2k views

  18. A way of shortening uvm_info filename to ONLY filename, not path/filename?

    By aquarioz,   
    • 8 replies
    • 17.9k views

  19. about uvm_reg::add_hdl_path_slice,can I assign a hdl varible declared as "wire""

    By commandos,   
    • 2 replies
    • 5.6k views

  20. Accessing a base test class data element in an extended class.

    By bap001,
    • 4 replies
    • 2.9k views

  21. accessing a generate block hierarchy

    By seyaleli22,
    • 0 replies
    • 3.4k views

  22. Accessing a memory element inside a memory model.

    By bap001,
    • 1 reply
    • 5.5k views

  23. Accessing arrays

    By antwens,
    • 0 replies
    • 1.1k views

  24. Accessing memory model from different components in the design

    By cooltoad,   
    • 0 replies
    • 1.1k views

  25. Accessing Memory model from various sequences

    By silverstream,
    • 6 replies
    • 5.4k views
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