Jump to content

UVM SystemVerilog Discussions

Use this forum when your question is about SystemVerilog language issues in the context of UVM. These can be about how to use a language feature is user code with the UVM or about language usage inside the UVM BCL.

596 topics in this forum

  1. UVM RAL | Getting the Register Name

    By Revanth,
    • 1 reply
    • 114 views

  2. Bug in UVM code using byte_en?

    By jie2024,
    • 0 replies
    • 55 views

  3. constraint dist 'others'

    By ljepson74,   
    • 4 replies
    • 6.8k views

  4. Warning-[PCWM-W] Port connection width mismatch

    By Rudresh,   
    • 0 replies
    • 164 views

  5. How memory interaction between C Language in SV or UVM

    By Subbi Reddy Manne,   
    • 1 reply
    • 455 views

  6. UVM Phase Jump

    By Hany Salah,
    • 4 replies
    • 226 views

  7. Mirrored value doesn't match the desired value while running default sequence uvm_reg_hw_reset_seq in ral test

    By Grace90,   
    • 0 replies
    • 299 views

  8. uvm_reg_predictor possible bug when using a 64bit register with 32bit interface

    By Kamil,
    • 0 replies
    • 130 views

  9. UVM_FATAL Errors

    By Hash,
    • 10 replies
    • 17k views

  10. How to continue a test after getting UVM error

    By Prathyusha G,
    • 1 reply
    • 756 views

  11. How to set parameterized sequcence as default sequence with +uvm_set_default_sequence ?

    By Jaor Ma,   
    • 1 reply
    • 362 views

  12. Is the UVM write_* imp port function by default a static function?

    By liyd,
    • 2 replies
    • 336 views

  13. Is data written on register used for APB protocol

    By M Prasanth,
    • 2 replies
    • 359 views

  14. How create mutiple uvm_component instances of uvm_component array?

    By mrforever,
    • 4 replies
    • 6.5k views

  15. UVM verification... illegal assignment

    By Ravi_3,
    • 1 reply
    • 545 views

  16. Uvm factory registration disambiguation

    By bradpinn,   
    • 1 reply
    • 412 views

  17. Relationship between PSEL and PENABLE signals in the APB Protocol.

    By P.Ksagar,   
    • 1 reply
    • 478 views

  18. Argument problem of uvm_mem_region::burst_read() in uvm-1.2

    By Leon,   
    • 1 reply
    • 344 views

  19. uvm_report_object -- why only uvm_component based classed are derived from uvm_report and not uvm_sequence_item/uvm_transaction

    By dips1000,
    • 2 replies
    • 359 views

  20. Package for parametric design

    By iidolevy,
    • 4 replies
    • 1.2k views

  21. UVM with AMS: Best practice for handling OOMR DUT probes with different net types

    By Paul Miller,
    • 2 replies
    • 606 views

  22. Simulation hang due to "run_phase" not exiting

    By ankurraj,
    • 4 replies
    • 2.8k views

  23. How to disable fork join or fork join_any after executed particular thread or process

    By Subbi Reddy Manne,
    • 2 replies
    • 1.1k views

  24. Interface not being loaded into config db correctly

    By LastHorizon,
    • 2 replies
    • 1.4k views

  25. Preload all the DUT

    By Peter_vertlib,
    • 0 replies
    • 357 views
×
×
  • Create New...