UVM Simulator Specific Issues

180 topics in this forum

1. VHDL entity in UVM

   By Naresh Raghava R, January 10, 2014   

   • VHDL UVM
   • 1 reply
   • 1.9k views
   • 
   • hbeck
   • February 2, 2015

2. syntax error in VCS

   By kieunguyen, November 25, 2014
   • 2 replies
   • 13.3k views
   • 
   • hbeck
   • February 2, 2015

3. Unable to link UVMC Lib?

   By Dhaval_Shah_, January 9, 2015
   • 1 reply
   • 2.2k views
   • 
   • apfitch
   • January 10, 2015

4. SV Constraints Failure due to rand variable assigned constant value

   By rashmikant.nu@gmail.com, December 4, 2014
   • 3 replies
   • 7.2k views
   • 
   • apfitch
   • December 7, 2014

5. running Questasim 10.2c in Cygwin using qverilog command for uvm-1.1d

   By chandan, November 9, 2014   

   • questasim
   • cygwin
   • (and 2 more)

     Tagged with:

     • questasim
     • cygwin
     • uvm-1.1d
     • qverilog
   • 5 replies
   • 5.4k views
   • 
   • chandan
   • November 24, 2014

6. uvm-1.2 uvm_dpi.cc compile errors using questasim 10.2c

   By Roman, October 16, 2014
   • 6 replies
   • 14.6k views
   • 
   • dave_59
   • October 20, 2014

7. UVM Register Assistant, No vreguvm -gui command

   By leapoo, July 24, 2014   

   • UVM
   • register assistant
   • 4 replies
   • 5k views
   • 
   • cgales
   • September 25, 2014

8. Unable to load the implicit shared object

   By sidharth.sankar77, September 3, 2014   

   • uvm
   • ncsim
   • (and 2 more)

     Tagged with:

     • uvm
     • ncsim
     • incisive
     • cadence
   • 1 reply
   • 3.1k views
   • 
   • uwes
   • September 8, 2014

9. How to set hdl path for fields in Cadence uvm_rgm?

   By adyashrotriya, November 15, 2011
   • 2 replies
   • 4.4k views
   • 
   • Euphemia
   • September 3, 2014

10. Can I detect UVM generated randomize transactions in waveform by Mentor tools?

    By leapoo, August 12, 2014
    • 1 reply
    • 2.7k views
    • 
    • wszhong631
    • September 2, 2014

11. Incompatible complex type usage error from VCS; Questa is OK

    By mea1201, July 9, 2014
    • 5 replies
    • 9.1k views
    • 
    • uwes
    • July 11, 2014

12. emacs auto-indent for verilog-mode messes up when 'class' used as other than SV keyword

    By ljepson74, June 18, 2014   

    • emacs
    • indentation
    • (and 1 more)

      Tagged with:

      • emacs
      • indentation
      • keyword
    • 3 replies
    • 7.5k views
    • 
    • ljepson74
    • June 20, 2014

13. Recursive generation of uvm reg models using ralfgen

    By fbochud, March 27, 2014   

    • ralf
    • regmodel
    • (and 1 more)

      Tagged with:

      • ralf
      • regmodel
      • ralfgen
    • 3 replies
    • 5.4k views
    • 
    • fbochud
    • June 5, 2014

14. Can't record dynamic array in sequence item in QuestaSim 10.3a_1

    By enchanter, May 26, 2014   

    • uvm_field_array_int
    • dynamic array
    • (and 3 more)

      Tagged with:

      • uvm_field_array_int
      • dynamic array
      • uvm_sequence_item
      • recording
      • questasim
    • 1 reply
    • 3.4k views
    • 
    • dave_59
    • May 27, 2014

15. Cadence: Incisive Enterprise Simulator vs. Incisive Unified Simulator - difference?

    By ljepson74, April 7, 2014   

    • Cadence
    • IUS
    • (and 4 more)

      Tagged with:

      • Cadence
      • IUS
      • IES
      • Incisive
      • Incisive Enterprise Simulator
      • Incisive Unified Simulator
    • 1 reply
    • 11.2k views
    • 
    • Adam Sherilog
    • May 5, 2014

16. uvm_re_match

    By love, April 25, 2014
    • 1 reply
    • 3.3k views
    • 
    • uwes
    • April 28, 2014

17. UVM 1.1d in QuestaSim with -pedanticerrors

    By tudor.timi, April 25, 2014
    • 1 reply
    • 1.5k views
    • 
    • dave_59
    • April 25, 2014

18. why 'payloadsegment[0]' is not a legal c identifier name,but payloadseqment_0_ ?!

    By wszhong631, March 19, 2014   

    • questasim10.2b/10.2c/10.1d
    • 2 replies
    • 2.6k views
    • 
    • wszhong631
    • March 20, 2014

19. Trouble running Questasim 10.0a with simple UVM example

    By cliffc, March 6, 2011
    • 9 replies
    • 17.2k views
    • 
    • chandan
    • March 17, 2014

20. transaction counter from waveform file

    By alfonsoamarco, March 3, 2014   

    • transaction
    • waveform
    • (and 1 more)

      Tagged with:

      • transaction
      • waveform
      • systemverilog
    • 0 replies
    • 1.7k views
    • 
    • alfonsoamarco
    • March 3, 2014

21. problem about debug_all and debug_pp of vcs

    By mrforever, February 18, 2014   

    • debug_all
    • debug_pp，
    • (and 1 more)

      Tagged with:

      • debug_all
      • debug_pp，
      • vcs
    • 1 reply
    • 7.6k views
    • 
    • apfitch
    • February 21, 2014

22. Best Technique to Measure Simulation Times using VCS

    By cliffc, January 3, 2014   

    • VCS performance
    • 1 reply
    • 8.7k views
    • 
    • adielkhan
    • February 6, 2014

23. Probing UVM classes in IUS 12.20.004

    By eyafe, January 11, 2014   

    • probe
    • simvision
    • (and 1 more)

      Tagged with:

      • probe
      • simvision
      • uvm
    • 1 reply
    • 3.7k views
    • 
    • uwes
    • January 13, 2014

24. Best Technique to Measure Simulation Times using Cadence Incisive

    By cliffc, January 3, 2014   

    • Cadence Incisive performance
    • 2 replies
    • 8.2k views
    • 
    • uwes
    • January 7, 2014

25. Best Technique to Measure Simulation Times using QuestaSim

    By cliffc, January 3, 2014   

    • QuestaSim performance
    • 3 replies
    • 4.5k views
    • 
    • Hans64
    • January 4, 2014