Jump to content

UVM (Pre-IEEE) Methodology and BCL Forum

Forum for posting questions about the pre-IEEE UVM library and its application to verification environments. 

932 topics in this forum

  1. set_type_override and set_inst_override usage inconsistency

    By chintanm86,
    • 2 replies
    • 30 views

  2. UVM factory usage recommendation inconsistent with base class implementation.

    By aelms,
    • 0 replies
    • 142 views

  3. uvm_comparer::compare_field_int() False Pass with size

    By aelms,
    • 0 replies
    • 184 views

  4. UVM Reg Model: access register error using bitbash seq because of predictor

    By Chris Le,
    • 2 replies
    • 582 views

  5. How to send sequence instead of stream of sequence_item?

    By soloist_huaxin,
    • 0 replies
    • 197 views

  6. uvm_object::set_int_local for static integer array

    By Robert.g.Liu,
    • 1 reply
    • 353 views

  7. Two sequences getting sequencer.lock grant in the same simulation cycle

    By b0rna,   
    • 0 replies
    • 428 views

  8. UVM register model: Field access and bus2reg

    By joniale,   
    • 2 replies
    • 1,142 views

  9. UVM register access with multiple masters to same register model

    By qwerty,
    • 3 replies
    • 683 views

  10. How to set a virtual interface of a VIP from SoC tb top

    By rudra2255,   
    • 0 replies
    • 507 views

  11. What would be the strategy to verify

    By karandeep963,
    • 1 reply
    • 585 views

  12. uvm_mem depth configuration

    By qwerty,
    • 1 reply
    • 455 views

  13. Problem about Setting UVM severity

    By thanhvanchi,
    • 1 reply
    • 693 views

  14. issues about Construction a verification environment for specific modules

    By thanhvanchi,
    • 1 reply
    • 602 views

  15. Are there any recommendations/guidelines on using UVM run sub phases?

    By mramdas,   
    • 0 replies
    • 742 views

  16. Complicated Register Modeling with uvm_reg

    By Logger,   
    • 0 replies
    • 1,464 views

  17. Why we get SEQREQZMB when jumping to another phase

    By zhiharev,
    • 2 replies
    • 684 views

  18. Instance override RAL adapter transaction objects?

    By kaushalmodi,   
    • 7 replies
    • 937 views

  19. What is a proper way to set fields and update register in uvm register model?

    By timothy,   
    • 1 reply
    • 1,266 views

  20. Query related to UVM_RAL_REG model.

    By Kameshwar Rao,
    • 1 reply
    • 670 views

  21. Usage of get_hdl_path() for backdoor register access

    By gaurav_brcm,
    • 0 replies
    • 998 views

  22. RAL mapping reg_field to another reg_field

    By defmaxou,
    • 1 reply
    • 494 views

  23. priority for uvm_reg transactions

    By proo,   
    • 0 replies
    • 853 views

  24. Communication between uvm_sequence and uvm_component

    By amar712,   
    • 3 replies
    • 1,112 views

  25. multiple maps on ral class

    By elihai,   
    • 0 replies
    • 815 views
×