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UVM (Pre-IEEE) Methodology and BCL Forum

Forum for posting questions about the pre-IEEE UVM library and its application to verification environments. 

931 topics in this forum

  1. UVM factory usage recommendation inconsistent with base class implementation.

    By aelms,
    • 0 replies
    • 106 views

  2. uvm_comparer::compare_field_int() False Pass with size

    By aelms,
    • 0 replies
    • 148 views

  3. UVM Reg Model: access register error using bitbash seq because of predictor

    By Chris Le,
    • 2 replies
    • 492 views

  4. How to send sequence instead of stream of sequence_item?

    By soloist_huaxin,
    • 0 replies
    • 166 views

  5. uvm_object::set_int_local for static integer array

    By Robert.g.Liu,
    • 1 reply
    • 312 views

  6. Two sequences getting sequencer.lock grant in the same simulation cycle

    By b0rna,   
    • 0 replies
    • 383 views

  7. UVM register model: Field access and bus2reg

    By joniale,   
    • 2 replies
    • 1,021 views

  8. UVM register access with multiple masters to same register model

    By qwerty,
    • 3 replies
    • 633 views

  9. How to set a virtual interface of a VIP from SoC tb top

    By rudra2255,   
    • 0 replies
    • 464 views

  10. What would be the strategy to verify

    By karandeep963,
    • 1 reply
    • 551 views

  11. uvm_mem depth configuration

    By qwerty,
    • 1 reply
    • 428 views

  12. Problem about Setting UVM severity

    By thanhvanchi,
    • 1 reply
    • 635 views

  13. issues about Construction a verification environment for specific modules

    By thanhvanchi,
    • 1 reply
    • 557 views

  14. Are there any recommendations/guidelines on using UVM run sub phases?

    By mramdas,   
    • 0 replies
    • 696 views

  15. Complicated Register Modeling with uvm_reg

    By Logger,   
    • 0 replies
    • 1,422 views

  16. Why we get SEQREQZMB when jumping to another phase

    By zhiharev,
    • 2 replies
    • 619 views

  17. Instance override RAL adapter transaction objects?

    By kaushalmodi,   
    • 7 replies
    • 899 views

  18. What is a proper way to set fields and update register in uvm register model?

    By timothy,   
    • 1 reply
    • 1,153 views

  19. Query related to UVM_RAL_REG model.

    By Kameshwar Rao,
    • 1 reply
    • 626 views

  20. Usage of get_hdl_path() for backdoor register access

    By gaurav_brcm,
    • 0 replies
    • 944 views

  21. RAL mapping reg_field to another reg_field

    By defmaxou,
    • 1 reply
    • 477 views

  22. priority for uvm_reg transactions

    By proo,   
    • 0 replies
    • 817 views

  23. Communication between uvm_sequence and uvm_component

    By amar712,   
    • 3 replies
    • 1,052 views

  24. multiple maps on ral class

    By elihai,   
    • 0 replies
    • 764 views

  25. Turn off `uvm_info messages

    By amar712,   
    • 3 replies
    • 1,273 views
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