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UVM (Pre-IEEE) Methodology and BCL Forum

Forum for posting questions about the pre-IEEE UVM library and its application to verification environments. 

934 topics in this forum

  1. get_starting_phase() vs starting seq with uvm_config_db

    By DV-E,
    • 0 replies
    • 54 views

  2. Address Map as submap to multiple address maps

    By Anil Kumar,   
    • 2 replies
    • 65 views

  3. set_type_override and set_inst_override usage inconsistency

    By chintanm86,
    • 2 replies
    • 114 views

  4. UVM factory usage recommendation inconsistent with base class implementation.

    By aelms,
    • 0 replies
    • 179 views

  5. uvm_comparer::compare_field_int() False Pass with size

    By aelms,
    • 0 replies
    • 222 views

  6. UVM Reg Model: access register error using bitbash seq because of predictor

    By Chris Le,
    • 2 replies
    • 665 views

  7. How to send sequence instead of stream of sequence_item?

    By soloist_huaxin,
    • 0 replies
    • 226 views

  8. uvm_object::set_int_local for static integer array

    By Robert.g.Liu,
    • 1 reply
    • 400 views

  9. Two sequences getting sequencer.lock grant in the same simulation cycle

    By b0rna,   
    • 0 replies
    • 463 views

  10. UVM register model: Field access and bus2reg

    By joniale,   
    • 2 replies
    • 1,278 views

  11. UVM register access with multiple masters to same register model

    By qwerty,
    • 3 replies
    • 739 views

  12. How to set a virtual interface of a VIP from SoC tb top

    By rudra2255,   
    • 0 replies
    • 547 views

  13. What would be the strategy to verify

    By karandeep963,
    • 1 reply
    • 618 views

  14. uvm_mem depth configuration

    By qwerty,
    • 1 reply
    • 492 views

  15. Problem about Setting UVM severity

    By thanhvanchi,
    • 1 reply
    • 749 views

  16. issues about Construction a verification environment for specific modules

    By thanhvanchi,
    • 1 reply
    • 637 views

  17. Are there any recommendations/guidelines on using UVM run sub phases?

    By mramdas,   
    • 0 replies
    • 779 views

  18. Complicated Register Modeling with uvm_reg

    By Logger,   
    • 0 replies
    • 1,489 views

  19. Why we get SEQREQZMB when jumping to another phase

    By zhiharev,
    • 2 replies
    • 747 views

  20. Instance override RAL adapter transaction objects?

    By kaushalmodi,   
    • 7 replies
    • 985 views

  21. What is a proper way to set fields and update register in uvm register model?

    By timothy,   
    • 1 reply
    • 1,371 views

  22. Query related to UVM_RAL_REG model.

    By Kameshwar Rao,
    • 1 reply
    • 705 views

  23. Usage of get_hdl_path() for backdoor register access

    By gaurav_brcm,
    • 0 replies
    • 1,057 views

  24. RAL mapping reg_field to another reg_field

    By defmaxou,
    • 1 reply
    • 515 views

  25. priority for uvm_reg transactions

    By proo,   
    • 0 replies
    • 890 views
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