Jump to content

UVM (Pre-IEEE) Methodology and BCL Forum

Forum for posting questions about the pre-IEEE UVM library and its application to verification environments. 

944 topics in this forum

  1. accessing register from more than one master

    By verifier,
    • 10 replies
    • 2.5k views

  2. umv 1.2: update of volatile reg fields

    By ejo,
    • 7 replies
    • 3.7k views

  3. RAL. Mirroring registers with the same addresses

    By zhiharev,
    • 6 replies
    • 4.8k views

  4. Register write() clobbers simultaneous access in multi-threaded testbench

    By jeremyr,
    • 2 replies
    • 1.8k views

  5. pass configuration object to sequence item

    By shail,
    • 7 replies
    • 7k views

  6. The difference between run_phase and main_phase in uvm_component

    By brxue,
    • 8 replies
    • 27.8k views

  7. multiple threads calling sequencer lock results in deadlock

    By Lawrence Said,   
    • 2 replies
    • 1.2k views

  8. how to pass a cmdline argument file when run simulation

    By xndwds313,
    • 11 replies
    • 19.3k views

  9. check while adding multiple fields with same name in same register

    By piyunaffi,
    • 0 replies
    • 284 views

  10. what is the intend of uvm_wait_for_nba_region?

    By qinhailiang,
    • 4 replies
    • 7.7k views

  11. uvm_reg_bit_bash_seq usage..

    By kiranbhaskar,
    • 8 replies
    • 16.6k views

  12. How to do two bus2reg operations for a single transaction

    By mon,
    • 2 replies
    • 728 views

  13. [Cadence] UVM-ML compiling issue with xcelium

    By hyperion007,
    • 1 reply
    • 532 views

  14. Wrong data width to access 128 bits register

    By paul,
    • 3 replies
    • 3.5k views

  15. The problem about uvm_reg_block

    By mrforever,
    • 3 replies
    • 6.7k views

  16. include_coverage not located message

    By loki,
    • 3 replies
    • 9.3k views

  17. problem with uvm ral read/mirror

    By assafgedalia,
    • 6 replies
    • 4.1k views

  18. `uvm_field_queue_object macro cause compiler error

    By ysimhony,   
    • 1 reply
    • 991 views

  19. Valid HDL path using DPI/VPI to access std_ulogic_vectors?

    By johannes.walter,
    • 6 replies
    • 10.6k views

  20. uvm_vreg increment issues

    By mbecker,   
    • 2 replies
    • 3.7k views

  21. UVM Backdoor access

    By Bazinga24,
    • 0 replies
    • 972 views

  22. Writing to a register when the status is UVM_NOT_OK

    By tudor.timi,
    • 3 replies
    • 7.3k views

  23. get after write doesn't update desired value, mirror gets updated correctly on read

    By Ai_Ar,
    • 0 replies
    • 559 views

  24. Controlling timescale with set_timeout

    By walkeranderson,
    • 5 replies
    • 5.2k views

  25. RAL Read Method

    By hvgbl,
    • 13 replies
    • 9.2k views
×
×
  • Create New...