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UVM (Pre-IEEE) Methodology and BCL Forum

Forum for posting questions about the pre-IEEE UVM library and its application to verification environments. 

944 topics in this forum

  1. UVM Register Model Burst Access

    By cschmitt,
    • 5 replies
    • 12.2k views

  2. uvm_reg::write updates regmodel in explicit prediction mode

    By Alex,
    • 6 replies
    • 12.4k views

  3. Adding a run-time phase example

    By walkeranderson,
    • 1 reply
    • 1.5k views

  4. my test stuck in uvm sequence `uvm_send()

    By jakfens,   
    • 1 reply
    • 1.8k views

  5. Simulation speed/efficiency

    By c4brian,
    • 7 replies
    • 2k views

  6. Random stability issue with `uvm_info and changing verbosity

    By bughound,   
    • 3 replies
    • 2.8k views

  7. uvm_config_db and hierarchical access

    By ljepson74,   
    • 3 replies
    • 3.9k views

  8. How to change verbosity of message during simulation?

    By mmistry,
    • 2 replies
    • 11.1k views

  9. uvm register implimentation for same register with different instances

    By leomoon85,   
    • 10 replies
    • 8k views

  10. Test / Sim Farm

    By c4brian,
    • 2 replies
    • 1.3k views

  11. Transaction Recording in Cadence

    By leelar,
    • 0 replies
    • 1.2k views

  12. referring/connecting env in a test

    By sathyakiran.p,   
    • 1 reply
    • 1.2k views

  13. uvm_component apply_config_settings method limitation

    By sylvainb,   
    • 2 replies
    • 2.3k views

  14. How do I raise objection to main phase in a component's run_phase()

    By walkeranderson,
    • 1 reply
    • 2.2k views

  15. How to file a bug?

    By syosil_jacob,   
    • 3 replies
    • 1.6k views

  16. uvm sequence for slave implementation

    By Madhu,   
    • 2 replies
    • 4.2k views

  17. using uvm_config_db::get inside a module

    By assafgedalia,
    • 1 reply
    • 3.5k views

  18. uvm_mem_mam request/reserve region size

    By walkeranderson,
    • 3 replies
    • 1.9k views

  19. uvm_builtin_reg_test_seq & default sequences

    By ljepson74,   
    • 2 replies
    • 4.1k views

  20. Different flow for uvm_recorder usage in uvm_component between UVM1.1 and UVM1.2

    By lianhuo,   
    • 0 replies
    • 1.7k views

  21. proper layering in an ethernet transaction class

    By c4brian,   
    • 18 replies
    • 9.8k views

  22. UVM Sequence Help

    By marcodemi,
    • 11 replies
    • 5.6k views

  23. extracting data from uvm_do_with macro

    By assafgedalia,
    • 4 replies
    • 2.1k views

  24. UVM Monitor help!!!

    By Hongnhattl,   
    • 21 replies
    • 8.2k views

  25. controlled transition from one phase to another

    By anshulgarg,   
    • 4 replies
    • 1.7k views
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