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UVM (Pre-IEEE) Methodology and BCL Forum

Forum for posting questions about the pre-IEEE UVM library and its application to verification environments. 

944 topics in this forum

  1. Randomization in Configuration Classes

    By Hany Salah,   
    • 4 replies
    • 4.2k views

  2. getting the number of UVM_ERROR/UVM_FATAL's

    By Mani,
    • 3 replies
    • 7.4k views

  3. passing sequence name on command line at run time

    By amitrana,
    • 4 replies
    • 2.9k views

  4. Register package - RGM vs other options

    By vkuvm,
    • 14 replies
    • 7.8k views

  5. Many-to-one on a TLM

    By TonyJ,
    • 6 replies
    • 3.5k views

  6. UVM IEEE v1.1 kill() and m_kill()

    By DV-E,
    • 0 replies
    • 730 views

  7. Pipelined RAL access

    By Kamlesh Shah,
    • 5 replies
    • 4.7k views

  8. UVM Register Field Coverage

    By graeme_jessiman,
    • 8 replies
    • 14.7k views

  9. X's in mirrored value (UVM hardware reset sequence)

    By gaurav_brcm,   
    • 8 replies
    • 5.4k views

  10. UVM's m_sequencer, p_sequencer, get_sequencer() and `uvm_declare_p_sequencer

    By cliffc,
    • 8 replies
    • 42.3k views

  11. how to report tool(vcs/ncsim..)/assertion related errors in UVM

    By sathyakiran.p,   
    • 4 replies
    • 5k views

  12. sequencer grab/ungrab not behaving according to specs

    By StefanoEsposito,
    • 1 reply
    • 1.2k views

  13. How to report bugs and enhancement requests for UVM

    By Tom_Alsop,
    • 3 replies
    • 5.9k views

  14. uvm_comparer::compare_field_int() False Pass with size

    By aelms,
    • 1 reply
    • 1.2k views

  15. UVM Reg Model: access register error using bitbash seq because of predictor

    By cuonghl,
    • 3 replies
    • 3.5k views

  16. Not able to configure thru +uvm_set_config_int:

    By kamboj,
    • 9 replies
    • 13.2k views

  17. get_starting_phase() vs starting seq with uvm_config_db

    By DV-E,
    • 0 replies
    • 3.3k views

  18. Address Map as submap to multiple address maps

    By Anil Kumar,   
    • 2 replies
    • 4.1k views

  19. set_type_override and set_inst_override usage inconsistency

    By chintanm86,
    • 2 replies
    • 4k views

  20. User defines frontdoor sequence can't support simultaneous accesses

    By ddayan14,
    • 10 replies
    • 4k views

  21. UVM factory usage recommendation inconsistent with base class implementation.

    By aelms,
    • 0 replies
    • 979 views

  22. Starting sequences on null sequencer?

    By cliffc,   
    • 8 replies
    • 15.9k views

  23. What is the proper way to trigger something when a uvm_reg field is written?

    By dwikle,
    • 7 replies
    • 24.9k views

  24. How to send sequence instead of stream of sequence_item?

    By soloist_huaxin,
    • 0 replies
    • 821 views

  25. cloning a register

    By assafgedalia,
    • 4 replies
    • 4.7k views
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