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SystemC Language

1,289 topics in this forum

  1. How to model output delay in SystemC like the Verilog non-blocking intra-assignment delay?

    By Shashank V M,
    • 2 replies
    • 933 views

  2. Can we assign value to sc_out while no obvious channel?

    By Ming,
    • 2 replies
    • 456 views

  3. Static sc_vpool objects to cause initialization order fiasco

    By Julien,   
    • 10 replies
    • 929 views

  4. unexpected VCD dump value

    By zidane,
    • 10 replies
    • 1k views

  5. ac_math test code compilation error

    By scsc,
    • 4 replies
    • 616 views

  6. Unable to initialize a vector of integers

    By otl0rz,
    • 4 replies
    • 902 views

  7. Enabling all warnings while compilation

    By Saikat,   
    • 3 replies
    • 421 views

  8. Variable declared as an 'inline' field in c++14

    By scsc,
    • 3 replies
    • 2.1k views

  9. Cannot notify an event from pthread to SystemC process

    By DS1701,
    • 6 replies
    • 1.7k views

  10. gcc 9.3.0

    By sumit_tuwien,
    • 2 replies
    • 630 views

  11. Instantiating SystemC module in Verilog: not seeing 1-cycle flop latency

    By coderoo,
    • 3 replies
    • 1.1k views

  12. Use SC_THREAD to realize delay

    By scsc,
    • 2 replies
    • 911 views

  13. Const array inside SC_CTOR

    By scsc,
    • 4 replies
    • 565 views

  14. double to sc_fix(ed) conversion

    By scsc,
    • 5 replies
    • 1.2k views

  15. C++20 Co-routines

    By Matthias Jung,
    • 0 replies
    • 819 views

  16. A model of an algorithm is created and tested. What is a way to make transition from the SystemC model to software implementation?

    By Igor Plastov,
    • 2 replies
    • 515 views

  17. Cannot write sc_signal

    By sumit_tuwien,
    • 7 replies
    • 830 views

  18. sc_fixed is undefined in VS 2017

    By scsc,
    • 2 replies
    • 980 views

  19. In constructor ‘tb::tb(sc_core::sc_module_name)’: ./tb.h:18:41: error: no match for call to ‘(sc_core::sc_fifo_in<myStruct_t>) (myStruct_t&)’

    By HTP,
    • 3 replies
    • 689 views

  20. SystemC communication with Linux kernel Module

    By zafir,
    • 4 replies
    • 1.2k views

  21. sc_report_handler affects the simulation itself

    By haase,
    • 4 replies
    • 780 views

  22. Need help to implement an interrupt controller simulator which handles the ISR

    By Jomon,   
    • 6 replies
    • 1.2k views

  23. Verifying SystemC model with Verilog/SV testbench

    By Nithin,
    • 3 replies
    • 1k views

  24. Data lost in transmission

    By bitfield,   
    • 4 replies
    • 666 views

  25. Question about expected behavior of wait event with delta cycle timeout

    By Yi-Chung.Lee,
    • 3 replies
    • 881 views
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