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  • Submitted: Jul 10 2012 07:46 PM
  • Last Updated: Dec 04 2013 02:27 PM
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Previous Versions

  • 19 Aug 2013 Download UVM-ML Open Architecture version 1.2.3
  • 30 May 2013 Download UVM-ML Open Architecture version 1.2.2
  • 10 Jul 2012 Download UVM ML

Download UVM-ML Open Architecture version 1.3

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UVM UVM-ML Multi-Language Verification



UVM-ML Open Architecture - version 1.3
Enabling Multi-Language and Multi-Framework Verification
December 4, 2013

General Overview
Universal Verification Methodology Multi-Language (UVM-ML) provides a modular solution for integrating verification components written in different languages into a unified and coordinated verification environment. It consists of an open source library that enables such integrations, and can be extended to support additional languages and methodologies.

This release of the UVM-ML implementation is the result of collaboration work between Advance Micro Devices, Inc., and Cadence Design Systems, Inc. It expands on the mature technology provided by Cadence in Incisive and in previous UVM-ML postings on UVMWorld. It is provided as open source under the Apache 2.0 license.

The main addition in version 1.3 is the support for UVM-ML configuration. In addition there are various enhancements in documentation, examples, installation, and tool versions supported. For the full listing please see the release-notes.txt file at the top of the release package. The release notes also provide the history of what was new in several previous versions.
UVM-ML Open Architecture (versions 1.2.2 and above) has significant enhancements over the earlier versions 1.0 and 1.1. The main enhancements and new features are:
  • Simulator independent and tested to run on several simulators
  • Architected to be highly modular and extensible
  • A new architecture providing a Backplane that connects Frameworks (where Frameworks can be of different languages or methodologies)
  • Three examples of language frameworks are provided: UVM-SV, UVM-e, UVM-SC
  • Enables creating a unified hierarchy of components of different frameworks
  • Support of TLM1 and TLM2 communication between all the provided frameworks
  • Enhanced synchronization of test phases and delegation of phasing control to a designated framework
  • and more...
This distribution includes the following main elements
  • Backplane implementation and API
  • Example frameworks and adapters (three provided: UVM-SV, UVM-e, and UVM-SC)
  • A few demos (showing all frameworks interacting) and a few smaller test examples
  • Docs directory with a Quick-Start, User Guides, and reference HTML docs
Information on all news and features can be found in the ml/docs/ directory.

This UVM-ML package is intended to serve as a basis for the verification community to collaboratively expand and evolve the multi-language verification methodology. It is currently available for early access and should not be considered complete. Please read the “Status, Use, and Disclaimers” section below for full details.

Where to Find Information
  • Where to start reading: point your web browser to ml/README.html
    The landing page provides links to installation directions, release notes, user guide, and more.
  • For feedback or questions: send email to support_uvm_ml@cadence.com
Platforms and Simulators
This release of UVM-ML should run on any simulator supporting one or more of the standard languages: IEEE 1800 (SystemVerilog), IEEE 1647 (e), and IEEE 1666 (SystemC). It was tested on the Linux operating system with various combinations of simulators and languages.

-------------------------------------------------------------------------------------------------------

UVM-ML Open Architecture: Status, Use, and Disclaimers
This section provides guidance and status regarding the use of the UVM Multi Language Open Architecture solution.

Status Statement: The UVM-ML Open Architecture package is an open source solution, developed jointly by AMD and Cadence. It is currently available for early access and should not be considered complete. We welcome feedback including suggestions for improvements. For any feedback or questions, please contact support_uvm_ml@cadence.com

Use and Disclaimers:
  • Licensing: This package is an open source library, protected under the Apache license (see legal clause at the bottom).
  • Access: This package is available as early access to the verification community, and therefore changes to its content and behavior should be expected.
  • Backward compatibility cannot be guaranteed. Changes are expected to take place when the verification community jointly refines the solution, to fit user requirements. We will aim, however, to provide help in adjusting to changes.
  • Quality: this package is still under development. It is being tested and regressed with Incisive 12.2 (latest available on download.cadence.com) before being released, but it was not tested on full scale projects, and therefore is not yet production by quality. This does imply that the user needs to be aware of the simulator version on which the solution is tested. AMD tested the open source solution on other commercial simulators. Issues reported to AMD and Cadence will be addressed.
  • Standardization: This package is not a standard. However, it is available as open source to all potential users.
  • Support: Since this is not a product, it does not have a committed level of product support. We will provide help via the UVMWorld community on Accellera where the source code is posted. For Cadence customers, Cadence will provide direct support as needed.
Note: the model described above is similar to how the very successful OVM and UVM-1.0ea (early version) were provided in the beginning. We believe you can gain significant value from access to this solution, and also be able to participate in developing it to ensure it addresses your needs.




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shuang.han@nxp.com
Aug 21 2013 07:37 AM

Hi,

 

I just tried to run the example in the package, but there are a lot of link error, can't find "ml_uvm_pkg.sv", etc. Could you give me some help for that, after read whole documents and can't get the example run is really depressed.

 

BR,

Han

Dear Han, 
This is probably some environmental issue we can easily solve together.

We will follow up with you offline (on the other thread you opened with support_uvm_ml@cadence.com).

Guy Mosenson @ Cadence

Photo
shuang.han@nxp.com
Aug 22 2013 05:22 AM

Hi,

 

Thank you very much for the quick support, the problem has been solved. It's indeed an environment issue and reason is the newest GCC version not support really well with NCSC. I can get the example running and will dig into it now. Thanks!

 

Best regards,

Han

Hi,

 

Below is the error generated while running the demo.sh for the prod_cons/sv_e/ or unified_hierarchy/e_sv/

 

irun: *E,BADSNL: The library /sim/debug_ip/user/x0012346/UVM_ML-1.3/ml/libs/uvm_e/12.2/4.4/64bit/libsn_sn_uvm_ml.so does not exist.
make[1]: *** [ies_proc_proper] Error 1
make[1]: Leaving directory `/sim/debug_ip/user/x0012346/UVM_ML-1.3/ml/examples/demos/prod_cons/sv_e'
make: *** [ies] Error 2

 

And the irun command options are:

TOOL:   irun(64)        12.20-s005: Started on Jan 27, 2014 at 15:07:53 CST
irun
        -l irun_ncsc_proc.64.log
        -f /sim/debug_ip/user/x0012346/UVM_ML-1.3/ml/tests/irun_uvm_ml.64.f
                -gcc_vers 4.4
                -spec /sim/debug_ip/user/x0012346/UVM_ML-1.3/ml/tools/specfiles/12.2/specfile.lnx86.gnu
.4.4.64bit
                -Wcxx,-I/sim/debug_ip/user/x0012346/UVM_ML-1.3/ml/frameworks/uvm/sc/ -Wld,-Xlinker
                -Wld,-rpath -Wld,-Xlinker
                -Wld,/sim/debug_ip/user/x0012346/UVM_ML-1.3/ml/libs/ncsc/12.2/4.4/64bit/ -Wcxx,-I/sim/d
ebug_ip/user/x0012346/UVM_ML-1.3/ml/frameworks/uvm/sc/
                -sv_lib /sim/debug_ip/user/x0012346/UVM_ML-1.3/ml/libs/backplane/4.4/64bit/libml_uvm.so
                -sv_lib /sim/debug_ip/user/x0012346/UVM_ML-1.3/ml/libs/backplane/4.4/64bit/libuvm_ml_bp
.so
                -L/sim/debug_ip/user/x0012346/UVM_ML-1.3/ml/libs/ncsc/12.2/4.4/64bit/
        -64bit
        ./test.sv
        -nosncomp
        +UVM_NO_RELNOTES
        -nocopyright
        -access rw
        -uvmhome /sim/debug_ip/user/x0012346/UVM_ML-1.3/ml/frameworks/uvm/sv/uvm-1.1c
        -exit
        -define UVM_REPORT_DISABLE_FILE_LINE
        -snshlib /sim/debug_ip/user/x0012346/UVM_ML-1.3/ml/libs/uvm_e/12.2/4.4/64bit/libsn_sn_uvm_ml.so
        -DSC_INCLUDE_DYNAMIC_PROCESSES
        -I/sim/debug_ip/user/x0012346/UVM_ML-1.3/ml/adapters/uvm_sc
        -I/sim/debug_ip/user/x0012346/UVM_ML-1.3/ml/adapters/uvm_sc/common
        -I/sim/debug_ip/user/x0012346/UVM_ML-1.3/ml/adapters/uvm_sc/ncsc
        -ml_uvm
        -top topmodule
        -define USE_UVM_ML_RUN_TES

 

basically Its not building the snapshot libsn_sn_uvm_ml.so at above dir, if any one knows about the cause for the above pls let us know.

 

Nagaraj Jaka
 


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