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Previous Versions

  • 26 May 2014 Download UVM-ML Open Architecture version 1.4
  • 04 Dec 2013 Download UVM-ML Open Architecture version 1.3
  • 19 Aug 2013 Download UVM-ML Open Architecture version 1.2.3
  • 30 May 2013 Download UVM-ML Open Architecture version 1.2.2
  • 10 Jul 2012 Download UVM ML

Download UVM-ML Open Architecture version 1.4.2

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UVM UVM-ML Multi-Language Verification



UVM-ML Open Architecture - version 1.4.2
Enabling Multi-Language and Multi-Framework Verification
Aug 13th, 2014

General Overview
Universal Verification Methodology Multi-Language (UVM-ML) provides a modular solution for integrating verification components written in different languages into a unified and coordinated verification environment. It consists of an open source library that enables such integrations, and can be extended to support additional languages and methodologies.

This release of the UVM-ML implementation is the result of collaboration work between Advance Micro Devices, Inc., and Cadence Design Systems, Inc. It expands on the mature technology provided by Cadence in Incisive and in previous UVM-ML postings on UVMWorld. It is provided as open source under the Apache 2.0 license.

This distribution includes the following main elements
  • Backplane implementation and API
  • Example frameworks and adapters (three provided: UVM-SV, UVM-e, and UVM-SC)
  • Several demos and high level examples (showing all frameworks interacting) and a few smaller feature examples (tests)
  • Docs directory with a Quick-Start, User Guides, and reference HTML docs
Information on all news and features can be found in the ml/docs/ directory.

This UVM-ML package is intended to serve as a basis for the verification community to collaboratively expand and evolve the multi-language verification methodology. It is currently available for early access and should not be considered complete. Please read the “Status, Use, and Disclaimers” section below for full details.

Where to Find Information
  • Where to start reading: point your web browser to ml/README.html
    The landing page provides links to installation directions, release notes, user guide, and more.
  • For feedback or questions: send email to support_uvm_ml@cadence.com
Platforms and Simulators
This release of UVM-ML should run on any simulator supporting one or more of the standard languages: IEEE 1800 (SystemVerilog), IEEE 1647 (e), and IEEE 1666 (SystemC). It was tested on the Linux operating system with various combinations of simulators and languages.

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UVM-ML Open Architecture: Status, Use, and Disclaimers
This section provides guidance and status regarding the use of the UVM Multi Language Open Architecture solution.

Status Statement: The UVM-ML Open Architecture package is an open source solution, developed jointly by AMD and Cadence. It is currently available for early access and should not be considered complete. We welcome feedback including suggestions for improvements. For any feedback or questions, please contact support_uvm_ml@cadence.com

Use and Disclaimers:
  • Licensing: This package is an open source library, protected under the Apache license (see legal clause at the bottom).
  • Access: This package is available as early access to the verification community, and therefore changes to its content and behavior should be expected.
  • Backward compatibility cannot be guaranteed. Changes are expected to take place when the verification community jointly refines the solution, to fit user requirements. We will aim, however, to provide help in adjusting to changes.
  • Quality: this package is still under development. It is being tested and regressed with all active versions of Incisive and with the Accellera OSCI simulator before being released, but is not yet considered full production quality. This does imply that the user needs to be aware of the simulator version on which the solution is tested. AMD tested the open source solution on other commercial simulators. Issues reported to AMD and Cadence will be addressed.
  • Standardization: This package is not a standard. However, it is available as open source to all potential users.
  • Support: Since this is not a product, it does not have a committed level of product support. We will provide help via the UVMWorld community on Accellera where the source code is posted. For Cadence customers, Cadence will provide direct support as needed.
Note: the model described above is similar to how the very successful OVM and UVM-1.0ea (early version) were provided in the beginning. We believe you can gain significant value from access to this solution, and also be able to participate in developing it to ensure it addresses your needs.
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What's new in each version
For the full listing and more details please see the release-notes.txt file at the top of the release package.
Please note that the items in red might require some changes on the user's side while upgrading to this version, please read these items carefully in the release notes.
  • 1.4.2:
    • Fully qualified with IES version 14.1
    • Enables usage of Cadence UVM extensions on top of UVM-ML OA
    • Support for UVM ML configuration tracing on the SV side, activated by the +UVM_CONFIG_DB_TRACE command-line option
    • Added new backplane API functions enabling the time notification (wakeup) service and updated the backplane API version number
    • Updated the sequence layering examples. The code is simplified and type conversion using mltypemap is demonstrated
    • Eliminated the UVM SV warnings
    • Mechanism to recognize whether OSCI was compiled with pthreads and compile the custom sc_simcontext.cpp accordingly
    • New examples showing basic TLM communication
    • Default installation is 32bit instead of 64bit
    • Setup and install scripts renamed
    • UVM-SC has been updated with a standalone phase controller that can run through the common and UVM phases. In addition user defined schedules, which can be synchronized with the standard UVM phases, are supported as well.
    • Enhanced UVM-SC to support run_test() in the SC-standalone mode (not collaborating with other frameworks)
  • 1.4:
    • Methodology and examples for sequence layering across languages
    • Enhancements in how unified hierarchy works
    • Support for uvm-1.1d (in place of uvm-1.1c)
    • Addition of a portable UVM-SC adapter.
  • 1.2.2:
    • Simulator independent and tested to run on several simulators
    • Architected to be highly modular and extensible
    • A new architecture providing a Backplane that connects Frameworks (where Frameworks can be of different languages or methodologies)
    • Three examples of language frameworks are provided: UVM-SV, UVM-e, UVM-SC
    • Enables creating a unified hierarchy of components of different frameworks
    • Multi-Language configuration
    • Support of TLM1 and TLM2 communication between all the provided frameworks
    • Enhanced synchronization of test phases and delegation of phasing control to a designated framework




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shuang.han@nxp.com
Aug 21 2013 07:37 AM

Hi,

 

I just tried to run the example in the package, but there are a lot of link error, can't find "ml_uvm_pkg.sv", etc. Could you give me some help for that, after read whole documents and can't get the example run is really depressed.

 

BR,

Han

Dear Han, 
This is probably some environmental issue we can easily solve together.

We will follow up with you offline (on the other thread you opened with support_uvm_ml@cadence.com).

Guy Mosenson @ Cadence

Photo
shuang.han@nxp.com
Aug 22 2013 05:22 AM

Hi,

 

Thank you very much for the quick support, the problem has been solved. It's indeed an environment issue and reason is the newest GCC version not support really well with NCSC. I can get the example running and will dig into it now. Thanks!

 

Best regards,

Han

Hi,

 

Below is the error generated while running the demo.sh for the prod_cons/sv_e/ or unified_hierarchy/e_sv/

 

irun: *E,BADSNL: The library /sim/debug_ip/user/x0012346/UVM_ML-1.3/ml/libs/uvm_e/12.2/4.4/64bit/libsn_sn_uvm_ml.so does not exist.
make[1]: *** [ies_proc_proper] Error 1
make[1]: Leaving directory `/sim/debug_ip/user/x0012346/UVM_ML-1.3/ml/examples/demos/prod_cons/sv_e'
make: *** [ies] Error 2

 

And the irun command options are:

TOOL:   irun(64)        12.20-s005: Started on Jan 27, 2014 at 15:07:53 CST
irun
        -l irun_ncsc_proc.64.log
        -f /sim/debug_ip/user/x0012346/UVM_ML-1.3/ml/tests/irun_uvm_ml.64.f
                -gcc_vers 4.4
                -spec /sim/debug_ip/user/x0012346/UVM_ML-1.3/ml/tools/specfiles/12.2/specfile.lnx86.gnu
.4.4.64bit
                -Wcxx,-I/sim/debug_ip/user/x0012346/UVM_ML-1.3/ml/frameworks/uvm/sc/ -Wld,-Xlinker
                -Wld,-rpath -Wld,-Xlinker
                -Wld,/sim/debug_ip/user/x0012346/UVM_ML-1.3/ml/libs/ncsc/12.2/4.4/64bit/ -Wcxx,-I/sim/d
ebug_ip/user/x0012346/UVM_ML-1.3/ml/frameworks/uvm/sc/
                -sv_lib /sim/debug_ip/user/x0012346/UVM_ML-1.3/ml/libs/backplane/4.4/64bit/libml_uvm.so
                -sv_lib /sim/debug_ip/user/x0012346/UVM_ML-1.3/ml/libs/backplane/4.4/64bit/libuvm_ml_bp
.so
                -L/sim/debug_ip/user/x0012346/UVM_ML-1.3/ml/libs/ncsc/12.2/4.4/64bit/
        -64bit
        ./test.sv
        -nosncomp
        +UVM_NO_RELNOTES
        -nocopyright
        -access rw
        -uvmhome /sim/debug_ip/user/x0012346/UVM_ML-1.3/ml/frameworks/uvm/sv/uvm-1.1c
        -exit
        -define UVM_REPORT_DISABLE_FILE_LINE
        -snshlib /sim/debug_ip/user/x0012346/UVM_ML-1.3/ml/libs/uvm_e/12.2/4.4/64bit/libsn_sn_uvm_ml.so
        -DSC_INCLUDE_DYNAMIC_PROCESSES
        -I/sim/debug_ip/user/x0012346/UVM_ML-1.3/ml/adapters/uvm_sc
        -I/sim/debug_ip/user/x0012346/UVM_ML-1.3/ml/adapters/uvm_sc/common
        -I/sim/debug_ip/user/x0012346/UVM_ML-1.3/ml/adapters/uvm_sc/ncsc
        -ml_uvm
        -top topmodule
        -define USE_UVM_ML_RUN_TES

 

basically Its not building the snapshot libsn_sn_uvm_ml.so at above dir, if any one knows about the cause for the above pls let us know.

 

Nagaraj Jaka
 

For easy installation and setup - take a look at the new video guide:

For easy installation and setup - take a look at the new video guide:

 

     UVM-ML Library Installation and Setup - in under 10 minutes.

 

You can find this video here ()

 

It provides a step-by-step walk through of downloading and installing the UVM-ML OA library.

This is followed by giving some details on where to find the documentation, as well as showing how to run one 
of the examples delivered with this library.
 
Guy Mosenson @ Cadence

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