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About This File

This document introduces UVM compliance checks defined for UVM verification environments. The compliance checklist was requested by corporations and UVM users wishing to ensure consistency, similar user experience, and compliance to the official UVM SystemVerilog User Guide and concepts. Static commercial tools such as DVT allow forcing these checks on user environments

The checks are divided into several categories:

* Packaging and Name Space Compliance Checks

* Architecture Compliance Checks

* Reset and Clock Compliance Checks

* Checking Compliance Checks

* Sequences Compliance Checks

* Messaging Compliance Checks

* Documentation Compliance Checks

* General Deliverables Compliance Checks

* End of Test Compliance Checks

* UVM-SV Specific Compliance Checks

For comments or questions please use the forums or send an email to uvm_contributions@cadence.com

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