48 files

  1. https://github.com/funningboy/smtdv
     
    SMTDV -Ver 1.1
    2016
     
    SMTDV is a lightweight verification framework based on UVM 1.1d,
    user can use/override it more easily to set up their verification environment at moudle level(functional check) and
    system level(cosim), that also supports 3rd part lib as sqlte3 db to export/import valid transactions.
     
    ----------------------------------------
    SMTDV flow overview
    ----------------------------------------
    kernel: base lib import, UVM_ML, systemc
    lib: uvc, common lib as middleware lib
    script: call, run, unittest
    dpi: 3rd part lib, sqlite3, stl, util lib
    designs: DUT
    test: test env
     

    -----------------------------------------
    Getting Started
    -----------------------------------------
    1. setup $SMTDV_HOME as default root
    %setenv $SMTDV_HOME <smtdv_install_area>
    %set $PATH = ${SMTDV_HOME}/script
     

    2. prepare .core file
    .core file uses section/token key to define preloading files and simulation args,
    that can be read more clear and easily as Makefile
     
    reserved sections
    [main] : define os.getenv, and opts
    [cores]: import dependey .cores
    [systemverilog]: define systemverilog include_files, include_dirs, and lib
    [verilog]: define verilog include_files, include_dirs, and lib
    [systemc]: define systemc include_files, include_dirs, and lib
    [sharedlib]: the sharedlib import as .so or *.a
    [ius]: use IUS as default simulator
    [mti]: use MTI as default simulator
     
    ex:
    lib/smtdv_common/smtdv_common.core
    lib/smtdv_apb_uvc/sim/smtdv_apb.core
     

    3. prepare required tool and lib
    % python >= 2.7.3
    % gcc, flex, yacc, sqlite3,
    % IUS >= 13.10, MTI >= 10.4
     

    4. build up 3rd part lib
    4.1 sqlite3 dpi interface build/test
    %cd dpi/sqlite3
    %./run.sh
    %./a.out
    4.1.2 run as systemverilog interface unittest
    % cd dpi/sqlite3/test
    %python ../../../script/run.py --file test_smtdv_sqlite3.core
     

    4.2 stl interface build/test
    4.2.1 stl dpi interface build/test,
    stl, it's a raw database to record bus(AXI/AHB/APB) transaction and layer info decoded as package
    and frame
     
    %cd dpi/stl
    %./run.sh
    %./a.out
    4.2.2 run as systemverilog interface unittest
    % cd dpi/stl/test
    %python ../../../script/run.py --file test_smtdv_stl.core
     

    5 UVC one on one (Master/Slave) basic test
    ref:
    ./lib/smtdv_apb_uvc/README
     
    6 module level test (cdnbus) test
    ref:
    ./lib

    14 downloads

    0 comments

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  2. This document is a printable version of the Easier UVM Coding Guidelines from Doulos. You are free to use these guidelines directly, to merge them into your own company-specific UVM coding guidelines, or merely to borrow some of the ideas.
     
    These coding guidelines are offered by Doulos for the benefit of the UVM community. They are not officially endorsed by Accellera.

    200 downloads

    0 comments

    Updated

  3. hi,
    this is the source code for the interface registry along with 3 examples and the paper/ppt from dvcon2015 illustrating the package. The package itself provides a simple scheme to connect DUV and TB using bind, interface self registration and a database.
    regards
    /uwe

    113 downloads

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  4. A generic UVM Scoreboard architecture supporting multiple models, packaging abstract queues and compare methods.

    241 downloads

    2 comments

    Updated

  5. The diagram here relates to UVM methodology discussion <http://forums.accellera.org/topic/2137-uvm-for-esl-dut-verification/#entry8274> on connecting UVM to an ES level model (i.e. SystemC)...

    41 downloads

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    Submitted

  6. Simple perl based UVM 1.2 UVC template generator

    93 downloads

    0 comments

    Submitted

  7. This is the updated UVM e Library, containing the e packages of:
    uvm_e/ - UVM e basic types
    uvm_scbd/ - UVM Scoreboard infrastructure, implemented in e
    vr_ad/ - UVM Registers & Memory package, implemented in e
    uvm_lp/ - UVM Low Power infrastructure, implemented in e
    eunit/ - e unit testing framework
    uvm_flow/ - base type of hubs and checkers
    Please refer to each package PACKAGE_README.txt for further information.

    42 downloads

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  8. This download contains a sample UVM environment that shows the use of IDesignSpec Free to generate a UVM Register Model. The input can be SystemRDL, IP-XACT, Word, Excel, XML etc.
    You can download the Free IDesignSpec Register Generator from here.
    You can use the included example as a ready reference to generate your own register model.
    You can use any or all of the IDesignSpec flavors: Word, Excel or Batch.

    240 downloads

    0 comments

    Updated

  9. A small package illustrating a method to perform
    UVC resets in UVM without phasing interaction.
    The package includes 4 examples and documentation showing the package in action
    /uwe

    473 downloads

    1 comment

    Updated

  10. Fixed few enum type-cast issues. Moved around the file ordering as needed by compilers. Added extra target for Riviera-Pro
    Fixed few issues in reg_models.
    Added Makefile targets for all 3 major EDA tools
    Steps to use
    -----------
    tar xvfz uvm_ref_flow_2014.02.tgz
    cd run_dir
    make vcs
    make qsta
    make cdn
    make rvra

    304 downloads

    0 comments

    Submitted

  11. This is the example code from the article "Flexible UVM Components: Configuring Bus Functional Models" in the Verification Horizon, June 2013.

    167 downloads

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  12. Hello,
    This contribution includes the updated examples for the second edition of the UVM Book: A Practical Guide to Adopting the Universal Verification Methodology (UVM) Second Edition.
    Enjoy!
    Kathleen Meade and Sharon Rosenberg

    1,838 downloads

    4 comments

    Submitted

  13. Fixed few enum type-cast issues. Moved around the file ordering as needed by compilers. Added extra target for Riviera-Pro
    Fixed few issues in reg_models.
    Added Makefile targets for all 3 major EDA tools
    Steps to use
    -----------
    tar xvfz uvm_ref_flow_2014.02.tgz
    cd run_dir
    make vcs
    make qsta
    make cdn
    make rvra

    825 downloads

    3 comments

    Updated

  14. This provided fine grain control of controlling verbosity of different IDs in same component.
    The default mechanism somehow does not work for more than one ID.

    91 downloads

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  15. The uvm_heartbeat is a sorely underused jem that cuts out wasted simulation time. What is it, how do you use it and why should you care? I will show you.


    406 downloads

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  16. Since the release of the UVM 1.0, one of the least documented features of the methodology has been the Run-Time Phasing solution. Due to this lack of documentation, many users were immediately turned off from trying to use this new area of the methodology. Even more unfortunate were those users who were brave enough to try and blaze the trail, but were quickly mired down in misuse, misinterpretation, and a general lack of support. This lack of documentation, combined with a general misunderstanding of what Run-time phasing was intended to solve, lead to many users labeling it as “unsafe”, and “overly complicated.”
    This document strives to remove the veil of confusion which the UVM’s Run-time phasing is wrapped in, by clarifying its intent and showing how easy it is to build very powerful stimulus.
     

    390 downloads

    1 comment

    Submitted

  17. When changing verbosity in the report_catcher (including setting verbosity when changing severity to UVM_INFO), the reporting does not work as expected. This fixes it.

    224 downloads

    0 comments

    Submitted

  18. Code examples that demonstrate the problems that parameterized interfaces present for reuseable VIP design and ways to overcome these limitations.

    593 downloads

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    Submitted

  19. UVM Connect is a package providing complete SystemC interop support for SystemVerilog UVM/OVM via TLM1/TLM2 to easily integrate models in either language, supports any compliant simulator, and works with both UVM and OVM.  Donated to Accellera by Mentor Graphics.

    The UVM Connect package builds on existing standards: SystemVerilog, SystemC and UVM, allowing TLM models in each language to communicate with each other.  The package also includes an API that allows SystemC to interact with, and control the execution of, UVM testbenches.
    With version 2.2, the UVM Connect package supports OVM as well as UVM, preserving an easy migration path for SystemC elements when the time comes to migrate from OVM the UVM.
    Who would use UVM Connect?

    The UVM Connect package enables a variety of use models as Verification IP developed in one language can be used by the other:
    reuse of SystemC models as reference models in SV using SystemC virtual platforms with SV RTL hardware descriptions integration of off-the-shelf VIP in either language using TLM1, TLM2, and Analysis Ports using SystemVerilog random stimulus or UVM sequences with a SystemC platform How is the Connection implemented?
    UVM Connect is open and standards-based.  It is implemented as a SystemVerilog package and a SystemC namespace.  These packages contain function calls that allow transactions to be passed between the two languages, using the SystemVerilog Direct Programming Interface (DPI), that enables SystemVerilog to make and accept C function calls.
    The API supports: one-line SV/DPI/SystemC socket connection mechanism for TLM1, TLM2 and Analysis Ports easy transaction conversion support, built-in Generic Payload support command API for interaction or control of the UVM testbench Compatibility:
    The UVM Connect package is compatible with any simulator, using the IEEE 1800 SystemVerilog and IEEE 1666 SystemC standards.  It has been tested by several verification teams in the industry and can accommodate various inter-language instantiation schemes.

    Support, training, documentation available at Verification Academy
     

    1,248 downloads

    1 comment

    Submitted

  20. UVM-ML Open Architecture - version 1.6
    Enabling Multi-Language and Multi-Framework Verification
    March, 2016
     
    General Overview
    Universal Verification Methodology Multi-Language (UVM-ML) provides a modular solution for integrating verification components written in different languages into a unified and coordinated verification environment. It consists of an open source library that enables such integrations, and can be extended to support additional languages and methodologies.
     
    This release of the UVM-ML implementation is the result of collaboration work between Advance Micro Devices, Inc., and Cadence Design Systems, Inc. It expands on the mature technology provided by Cadence in Incisive and in previous UVM-ML postings on UVMWorld. It is provided as open source under the Apache 2.0 license.
     
    This distribution includes the following main elements
    Backplane implementation and API Example frameworks and adapters (three provided: UVM-SV, UVM-e, and UVM-SC) Several demos and high level examples (showing all frameworks interacting) and a few smaller feature examples (tests) Docs directory with a Reference manual, User Guide and reference HTML docs

    Information on all news and features can be found in the ml/docs/ directory.
     

    This UVM-ML package is intended to serve as a basis for the verification community to collaboratively expand and evolve the multi-language verification methodology. Please read the “Status, Use, and Disclaimers” section below for full details.
     
    Where to Find Information
    Where to start reading: point your web browser to ml/README.html
    The landing page provides links to installation directions, release notes, user guide, and more. For feedback or questions: send email to support_uvm_ml@cadence.com An easy installation and Setup video guide is available You can checkout the update of David I. Long form Doulos at DVCon 2016 in the US. It relates to UVM-ML (along with other updates).

    Blog series:
    Multi-Language Verification Environment—Getting First Run in Few Minutes Multi-Language Verification Environment (#2) – Passing Items on TLM Ports, Using UVM ML Multi-Language Verification Environment (#3) – Connecting UVM Scoreboard to a Multi-Language Environment Multi-Language Verification Environment (#4)—Multi-Language Hierarchy Debugging Multi-Language Verification Environments

    Platforms and Simulators
    This release of UVM-ML should run on any simulator supporting one or more of the standard languages: IEEE 1800 (SystemVerilog), IEEE 1647 (e), and IEEE 1666 (SystemC). It was tested on the Linux operating system with various combinations of simulators and languages.
     

    -------------------------------------------------------------------------------------------------------
     
    UVM-ML Open Architecture: Status, Use, and Disclaimers
    This section provides guidance and status regarding the use of the UVM Multi Language Open Architecture solution.
     
    The UVM-ML Open Architecture package is an open source solution, developed jointly by AMD and Cadence. We welcome feedback including suggestions for improvements. For any feedback or questions, please contact support_uvm_ml@cadence.com
     
    Use and Disclaimers:
    Licensing: This package is an open source library, protected under the Apache license (see legal clause at the bottom). Access: This package is available as early access to the verification community, and therefore changes to its content and behavior should be expected. Backward compatibility cannot be guaranteed. Changes are expected to take place when the verification community jointly refines the solution, to fit user requirements. We will aim, however, to provide help in adjusting to changes. Quality: this package is still under development. It is being tested and regressed with all active versions of Incisive and with the Accellera OSCI simulator before being released. The user needs to be aware of the simulator version on which the solution is tested. AMD tested the open source solution on other commercial simulators. Issues reported to AMD and Cadence will be addressed. Standardization: This package is not a standard. However, it is available as open source to all potential users. Support: Since this is not a product, it does not have a committed level of product support. We will provide help via the UVMWorld community on Accellera where the source code is posted. For Cadence customers, Cadence will provide direct support as needed.

    Note: the model described above is similar to how the very successful OVM and UVM-1.0ea (early version) were provided in the beginning. We believe you can gain significant value from access to this solution, and also be able to participate in developing it to ensure it addresses your needs.
    -------------------------------------------------------------------------------------------------------
    What's new in each version
    For the full listing and more details please see the release-notes.txt file at the top of the release package.
    Please note that the items in red might require some changes on the user's side while upgrading to this version, please read these items carefully in the release notes.
    1.6: Fully qualified with IES versions 14.2,15.1 and 15.2. UVM-SV 1.2 is now fully supported (please read RELEASE_NOTES.txt under ml directory for more details). When working with Incisive 15.2, the user can take some steps in order to skip compiling the e part of the adapter (this might be important for users that compile other
    e code on top of Specman, like VIP). The steps are documented in the UVM-ML OA user guide under:
    "Linking the Specman UVM-e Adapter From Incisive Version 15.2 On". OSCI 2.3.1 is now supported instead of OSCI 2.3, meaning that the supported OSCI versions are: 2.3.1 and 2.2. gcc 4.8.3 is now supported
    [*]1.5.1:
    Fully qualified with IES versions 14.1,14.2 and 15.1. Early adopters UVM-SV 1.2 support for IES (please read RELEASE_NOTES.txt under ml directory for more details). UVM-ML tcl commands are now available from Specman with all supported simulators. UVM-ML tcl commands are renamed (they all start with uvm_ml prefix, followed by a space and the command name, e.g uvm_ml print_tree). The old names are still supported. Pre-compiled UVM-SC parts for IES were eliminated. Examples are enhanced and extended. Updated the Backplane API version number.
    [*]1.5:
    New debug commands in IES to print the UVM-ML tree, port connections, and port registrations. Brand-new documentation including User Guide, Reference Manual and more. Support for IES reset in UVM-ML environment. Support for sharing uvm_events and uvm_barriers between UVM-SV and UVM-SC. Support for +UVM_TESTNAME in all simulators and languages. Passing tlm_generic_payload transactions via analysis ports. Several ASI SystemC enhancements: Automated synchronization, ML-registering of SC TLM2 sockets. Reorganized examples to make them more useful. Enhanced and simplified installation and setup. Fully qualified with IES versions 13.2, 14.1, and 14.2.
    [*]1.4.4:
    "Phase Debug" feature, for setting breakpoints at the beginning or end of UVM-ML phases (see the Integrator User Guide for details). Currently this works only for IES. Added support for the generic UVM SV syntax, uvm_config_db#(T), so that it now works also for ML configuration Improved the way to run the demo examples and to learn how to run UVM-ML Reduced the amount of ML enabling modifications introduced into the local version of UVM-SV (1.1d), by enhancing the UVM-SV adapter implementation The e macro uvm_ml_stub_unit now directly sets unit attributes hdl_path() and agent(), thus saving the user a need to add auxiliary string fields Improved the handling of UVM-ML bitness (once users select 32 or 64 bit mode, the library and all examples will run in that mode) Enhanced sequence layering capabilities Enhanced the test_env.csh script to provide more validity testing of the user's environment and to provide better suggestions how to fix issues irun_uvm_ml.*.f option files were reorganized (including a name change): IES irun invocation options were grouped into several option files, reflecting the usage context, and adding comments to clarify their meaning This release might require some changes on the user's code while upgrading to this version, see details in the release_notes.txt”
    [*]1.4.2:
    Fully qualified with IES version 14.1 Enables usage of Cadence UVM extensions on top of UVM-ML OA Support for UVM ML configuration tracing on the SV side, activated by the +UVM_CONFIG_DB_TRACE command-line option Added new backplane API functions enabling the time notification (wakeup) service and updated the backplane API version number Updated the sequence layering examples. The code is simplified and type conversion using mltypemap is demonstrated Eliminated the UVM SV warnings Mechanism to recognize whether OSCI was compiled with pthreads and compile the custom sc_simcontext.cpp accordingly New examples showing basic TLM communication Default installation is 32bit instead of 64bit Setup and install scripts renamed UVM-SC has been updated with a standalone phase controller that can run through the common and UVM phases. In addition user defined schedules, which can be synchronized with the standard UVM phases, are supported as well. Enhanced UVM-SC to support run_test() in the SC-standalone mode (not collaborating with other frameworks)
    [*]1.4:
    Methodology and examples for sequence layering across languages Enhancements in how unified hierarchy works Support for uvm-1.1d (in place of uvm-1.1c) Addition of a portable UVM-SC adapter.
    [*]1.2.2:
    Simulator independent and tested to run on several simulators Architected to be highly modular and extensible A new architecture providing a Backplane that connects Frameworks (where Frameworks can be of different languages or methodologies) Three examples of language frameworks are provided: UVM-SV, UVM-e, UVM-SC Enables creating a unified hierarchy of components of different frameworks Multi-Language configuration Support of TLM1 and TLM2 communication between all the provided frameworks Enhanced synchronization of test phases and delegation of phasing control to a designated framework



    3,422 downloads

    8 comments

    Updated

  21. A simple integrated example test bench for people who want to learn UVM.
    This is pre-alpha, unreviewed and buggy code. If you use this as a basis for anything other than reviewing it for bugs then you're on your own.
    If you tape-out something based on this you will waste time and money.
    See the README for more information

    739 downloads

    0 comments

    Submitted

  22. The UVM Reference Flow version 1.1 has been updated to align with the Accellera uvm-1.1 release (uvm-1.1a). It applies the Universal Verification Methodology (UVM) to a Block and Cluster Verification in a SoC Design. The UVM Reference Flow was developed by Cadence to show the best practices for applying UVM to the verification of a block, a Universal Asynchronous Receiver Transmitter (UART). It then shows how to reuse the block level verification environment when verifying a cluster design (an APB subsystem) into which the UART is integrated along with other design components (viz. SPI, GPIO, Power Controller, Timers etc…).

    This contribution is not approved or endorsed by Accellera but may be of interest to UVM users as is true of other contributions.
    What’s New : This release of the UVM Reference Flow is completely aligned with the latest uvm-1.1 production library from Accellera and demonstrates the latest features including:
    - global resource database for configuration mechanism
    - UVM_REG methodology for register verification. The UVM_REG package is a part of uvm-1.1 release.
    This release also includes a UVM e Reference Flow which applies the Universal Verification Methodology in e (UVM-e developed by Cadence) to the same block and cluster level Verification of UART and APB subsystem. The sample verification environments (both block and cluster level) contain UVCs based on eRM as well as using UVM-e. Both eRM and UVM-e compatible UVC's can be nicely integrated together and can work seamlessly. Thus, it ensures that all existing eRM compliant environments need not to be re-coded to work with an UVM compatible environment. Usage of the UVM-e Scoreboard package is also included in this release.
    The UVM Reference Flow design is based on an Ethernet Switch System-on-Chip (SoC). The SoC has the following key design components
    1. An Opencores Open RISC Processor
    2. Opencores Ethernet Media Access controller (MAC)
    3. AMBA AHB network interconnect
    4. Address Look up table (ALUT)
    5. Support and Control functions. For instance power management and peripherals like UART, SPI, GPO, timer etc
    6. On-chip Memories and memory controller

    The UVM Reference Flow also includes the following key verification components
    1. AMBA AHB UVC (SV & e)
    2. AMBA APB UVC (SV & e)
    3. UART UVC (SV & e)
    4. GPIO UVC (SV & e)
    5. SPI  UVC (SV & e) 
    6. Register Memory Package (uvm_reg) from uvm-1.1 library
    7. UVM-e scoreboard
    Please look at the UVM Reference Flow user guide which can be found at
    For SV flow : <UVM Reference Flow Installation area>/doc/uvm_flow_topics/uvm_sv/uvm_sv_ref_flow_ug.pdf for more details.
    For e Flow : <UVM Reference Flow Installation area>/doc/uvm_flow_topics/uvm_e/uvm_e_ref_flow_ug.pdf for more details.
    Release Version :1.1
    The UVM Reference UVM Reference Flow 1.1 release is tested with UVM 1.1 Production Library (uvm-1.1) (from Accellera) and Incisive Enterprise Simulator (IES) 11.1 It should be possible to run the UVM Reference Flow on any IEEE 1800 and 1647 Compliant Simulator which supports UVM.
    For more information about using the UVM Reference Flow please contact uvm_ref@cadence.com.
     

    4,399 downloads

    1 comment

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  23. UVM user guide explains in detail how a model is integrated for a parallel interface. This paper discusses the use of UVM register classes when verifying register accesses through a serial port (e.g., JTAG) on the DUT.

    3,228 downloads

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  24. This contribution describes a "simple" methodology that allows for creating UVM Verification Components (UVCs) that have the flexibility to optionally be connected to other UVCs. This methodology helps promote easier vertical and horizontal reuse.  This topic was presented at Accellera Systems Initiative Day at DVCon in the UVM: Ready, Set, Deploy session.
    The contribution includes:
    (1) A stacking UVC UVM example that runs with the any of the 3 big EDA vendor simulators
    (2) A paper called "StackingUVCs.pdf" that describes the methodology and the accompanied example in detail
    To use:
    >>tar xvf stack_example.tgz
    Then read the "SIMPLE_README.txt" file for information on running the example and read the "StackingUVCs.pdf" for details on the methodology and a description of the example.

    For any issues or if you would like to learn more about Paradigm Works UVM methodlogies contact us at: pw-support@paradigm-works.com.
     

    760 downloads

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  25. Updated with a few bug fixes.  Two minor new features added with v1.10:
    -use_seqr : by default, no sequencer component is created, this switch willforce a custom uvm_sequencer component to be generated (not available with -one_file)
      -one_file : generate simple uvc in single file - for building small examples  

    1,150 downloads

    0 comments

    Submitted