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  3. maehne

    ELN Low pass filter

    Well, you will have to write a test bench, which provides your RC filter with some stimuli for transient simulation or sets up an AC analysis. However, I recommend you to have first a closer look to the fundamental concepts and ideas of SystemC AMS. A good introduction to SystemC AMS is provided by the SystemC AMS extensions User's Guide, which is part of the SystemC AMS extensions 1.0 release. Even though, this discusses only the features available sind SystemC AMS 1.0, it is a good start as SystemC AMS 2.0 and IEEE Std 1666.1 added mainly advanced features related to Dynamic TDF and bug fixes. Also, the SystemC AMS community pages provide some good links to introductory resources to get started with SystemC AMS.
  4. Roman Popov

    tlm_fifo nb_peek

    2.3.3 will be released next week w/o a fix. So most likely next one after 2.3.3
  5. vasu_c

    tlm_fifo nb_peek

    Thank you so much Roman and Philipp. Appreciate the work around suggested. Please can I know which release would contain this fix ?
  6. #include "systemc.h" #include "systemc-ams.h" SC_MODULE (lpf) { sca_eln::sca_terminal a; sca_eln::sca_terminal b; sca_eln::sca_r r1; sca_eln::sca_c c1; SC_CTOR(lpf) :a("a"),b("b"),r1("r1",10e3),c1("c1",100e-6),gnd("gnd") { r1.p(a); r1.n(b); c1.p(b); c1.n(gnd); } private: sca_eln::sca_node_ref gnd; }; hi to all i wrote this code for eln low pass filter how should i test it?
  7. StS

    UVM

    I assume that by this term an empty verification IP is meant. So you would have just to fill in specific functionality such as e.g. the driver interface, monitor interface, items, sequences, etc.
  8. Hi! This actually depends on how you implemented your agent and how you implemented its configuration abilities. This is more a general UVM design question and not strongly UVM-SystemC related.
  9. Those questions are covered in detail in paragraphs 14.1 and 14.2 of SystemC standard. Can't answer in a better way. TLM2.0 simulations are not cycle-accurate, so you don't have clock edge events. In AT modeling style you should call wait(delay) after each transport call. In LT modeling style all initiators are temporaly decoupled and can run ahead of simulation time, usually for a globally specified time quantum. For debugging you can use the same techinques as in cycle-accurate modeling: Source-level debugging with breakpoints and stepping Transaction and signal tracing Logging Comparing with RTL, debugging using waveform won't be that effective, because in AT/LT modeling state of model can change significantly in a single simulator/waveform step. Usually preffered way is combination of logging and source-level debug. Debugging TLM models is harder comparing to RTL. Also C++ is much more complex and error-prone comparing to VHDL/Verilog.
  10. Thank you Roman for helping! I am confused because TLM and systemc set lots of rules and standards, but it didn't say what can not be done by using c++. For example, can I inherit the payload interface and make my own payload class with stuffs I need and pass it through the nb_transport call. Would this make sense to you? Also, in the nb_transport, time is annotated by passing the delay with the trans object, how could I actually have a clock and have all the transactions follow the clock edge? I tried to use sc_method, but somewhere in the LRM says generic payload only works with sc_thread. Without the clock, how are the signals traced? If a bug or more bugs in the design, how could I debug it systematically? Back to RTL i would look at my simulation waveforms, but how to solve it under the systemc and tlm abstraction level? Thanks again! Best, Tyler Thanks again!
  11. Anil, The UVM committee knows of this limitation but our workaround suggestion would be exactly what you are doing with creating duplicate maps. A fix is on our to-do list. Thanks for posting, Mark
  12. TLM payload is used for untyped raw data transfers. Data format is usually a property of device. Let's consider an example: Initiator is CPU model, and target is Convolution filter accelerator. Accelerator accepts a 2d matrix (2d array) of coefficients as an input. Documentation of accelerator must specify a binary format of data, for example: coefficients are stored in row-major order, each coefficient is 8-byte signed integer. Using this documentation initiator converts 2d array into a raw data of tlm payload. And device model converts raw data back into 2d array. This is how it is usually done.
  13. Philipp A Hartmann

    tlm_fifo nb_peek

    Alternatively, as you don't seem to require the debug interface, you can change the port to: sc_port<tlm::tlm_get_peek_if<int> > target_port;
  14. Roman Popov

    tlm_fifo nb_peek

    Thanks for report. I will put this into SystemC bug tracker. Until it is fixed, you can use a workaround: target_port->tlm_get_peek_if<int>::nb_peek(b);
  15. SC_UNCHECKED_WRITERS also means allowing nasty race conditions.
  16. I tried to pass a 2d array of data through the generic payload. int a[10][10]; trans.set_data_ptr((unsigned char*) a); ... ... unsigned char* data = trans.get_data_ptr; Then if i get the data ptr at my target, I would have a 1d array. I guess this is not doable here. I wonder what if I use the tlm extension to add a customized extension to generic payload, and have a local 2d array there and I have access it through the generic payload instance? Can i write a method in extension class that takes a 2d array as a argument and then assign it to the local one so i can manipulate it at my initiator and a method that would return it so that i can get it at my target? Thank you in advance for any clarification and time. T
  17. Hi johnmac, What you try to do is conceptually wrong: Ready and Valid should be two separate signals. Initiator drives the Valid signal, and responder drives the Ready. There is an example of ready-valid channel that comes together with SystemC, check in systemc/examples/sysc/2.3/sc_rvd If your final goal is synthesizable code, then both Mentor and Cadence synthesis tools already have it implemented in their libraries. Check vendor documentation. If you still want to simulate your design, you can try to use SC_UNCHECKED_WRITERS instead of SC_MANY_WRITERS. This will disable a check for multiple drivers in a single delta cycle.
  18. Thanks for the response @Eyck I followed your suggestions, and did something like this. Pls bear with me if I am being thick 😉 I am running into an error that looks like this: SystemC 2.3.1-Accellera --- Sep 7 2015 10:55:18 Copyright (c) 1996-2014 by all Contributors, ALL RIGHTS RESERVED Initator started Waiting Responder started Error: (E115) sc_signal<T> cannot have more than one driver: signal `signal_0' (sc_signal) first driver `init.func1' (sc_thread_process) second driver `resp.func2' (sc_thread_process) first conflicting write in delta cycle 1 In file: ../../../../src/sysc/communication/sc_signal.cpp:73 In process: resp.func2 @ 0 s I have the interfacing signal declared with SC_MANY_WRITERS. sc_signal<hs, SC_MANY_WRITERS> intf; #include <systemc.h> #include <iostream> struct hs { bool ready; bool valid; inline friend void SetReady(hs & pt, bool value) { pt.ready = value; } inline friend void SetValid(hs & pt, bool value) { pt.valid = value; } inline bool operator == (const hs & rhs) const { return false; } inline hs& operator = (const hs& rhs) { ready = rhs.ready; valid = rhs.valid; return *this; } inline friend void sc_trace(sc_trace_file *tf, const hs & v, const std::string& NAME ) { sc_trace(tf,v.ready, NAME + ".ready"); sc_trace(tf,v.valid, NAME + ".valid"); } inline friend ostream& operator << ( ostream& os, hs const & v ) { os << v.ready << " " << v.valid << endl; return os; } }; SC_MODULE(initiator) { sc_in <bool> clk; sc_inout<hs> handshake; void func1(); SC_CTOR(initiator) { SC_THREAD(func1); sensitive << clk; dont_initialize(); }; }; SC_MODULE(responder) { sc_in <bool> clk; sc_inout<hs> handshake; void func2(); SC_CTOR(responder) { SC_THREAD(func2) sensitive << clk; dont_initialize(); }; }; void initiator::func1() { cout << "Initator started\n"; hs tmp_hs; tmp_hs = handshake; SetValid(tmp_hs, false); handshake = tmp_hs; while(true) { tmp_hs = handshake.read(); if (tmp_hs.ready == false) { cout << "Waiting" << endl; wait(clk->posedge_event()); } else { break; } } tmp_hs = handshake; SetValid(tmp_hs, true); handshake = tmp_hs; wait(clk->posedge_event()); cout << "Initator valid set to HIGH\n"; } void responder::func2() { int sleep_i; hs tmp_hs; cout << "Responder started\n"; tmp_hs = handshake; SetReady(tmp_hs, false); handshake = tmp_hs; for(sleep_i = 0; sleep_i < 40; sleep_i++) wait(clk->posedge_event()); tmp_hs = handshake; SetReady(tmp_hs, true); handshake = tmp_hs; }
  19. As an alternate solutions, we have developed methods which will create a duplicate uvm_reg_map for any given uvm_reg_map. Another solution, is to extend IP reg block and create duplicate maps, size of this duplicate map will be controlled at higher levels and do a factory override. Does, UVM recommend any solution for this?
  20. Actually, I forgot to answer your quesions, so here we go. Can struct contain signals that flow in different directions? Yes, of course. struct is just a a wrapper which handles datatype as one Can sc_inout<struct T> also map directly to another module with the same sc_inout<struct T>? Well, ports need to connect to signals, there is no way to connect 2 ports directly except you do a hierarchical binding Am I also setting the struct contents correctly? This I answer in the last post.
  21. The problem is that you do not write to the signal carrying the struct (and therefore you do not trigger any event). The SetValid() call implicitly triggers a read (thru the overloaded cast) but you never write back to the signal. Either you change the use of SetValid (and SetReady): { hs data = handshake.read(); SetValid(hs, false); handshake.write(data); } Here the call to wriite() trigges the respective events. The other option is to change SetValid() to take a signal reference and move the code into the function. Best regards
  22. I am using sc_inout<struct T> to emulate a handshake flow of 'ready' and 'valid'. 'ready' flows in Responder --> Initiator and 'valid' flows in Initiator --> Responder. The setup doesnt work and causes the simulation to hang at 'Waiting'. I don't get a waveform because the simulation never completes. I suspect Can someone tell me if there are things I am overlooking: Can struct contain signals that flow in different directions? Can sc_inout<struct T> also map directly to another module with the same sc_inout<struct T>? Am I also setting the struct contents correctly? I eventually want to expand this handshake to several more signals (20+ more) which will connect directly to another module. Any alternate suggestions will also help a lot. #include <systemc.h> #include <iostream> struct hs { bool ready; bool valid; inline friend void SetValid(hs & pt, bool value) { pt.valid = value; } inline friend void SetReady(hs & pt, bool value) { pt.ready = value; } // inline friend bool GetReady(const hs& pt) { inline friend bool GetReady(const hs & pt) { return pt.ready; } inline friend bool GetValid(const hs & pt) { return pt.valid; } inline bool operator == (const hs & rhs) const { return false; } inline hs& operator = (const hs& rhs) { ready = rhs.ready; valid = rhs.valid; return *this; } inline friend void sc_trace(sc_trace_file *tf, const hs & v, const std::string& NAME ) { sc_trace(tf,v.ready, NAME + ".ready"); sc_trace(tf,v.valid, NAME + ".valid"); } inline friend ostream& operator << ( ostream& os, hs const & v ) { os << v.ready << " " << v.valid << endl; return os; } }; SC_MODULE(initiator) { sc_in <bool> clk; sc_inout<hs> handshake; void func1(); SC_CTOR(initiator) { SC_THREAD(func1); sensitive << clk; dont_initialize(); }; }; SC_MODULE(responder) { sc_in <bool> clk; sc_inout<hs> handshake; void func2(); SC_CTOR(responder) { SC_THREAD(func2) sensitive << clk; dont_initialize(); }; }; void initiator::func1() { cout << "Initator started\n"; SetValid((hs&)handshake, false); while(GetReady(handshake) == false) { cout << "Waiting" << endl; wait(clk->posedge_event()); } SetValid((hs&)handshake, true); cout << "Initator valid set to HIGH\n"; } void responder::func2() { int sleep_i; SetReady((hs&)handshake, false); cout << "Responder started\n"; for(sleep_i = 0; sleep_i < 40; sleep_i++) wait(clk->posedge_event()); SetReady((hs&)handshake, true); } The instantiation looks like this: int sc_main(int argc, char* argv[]) { sc_clock clock("clock", 10, SC_NS); sc_signal<hs, SC_MANY_WRITERS> intf; initiator init("init"); responder resp("resp"); init.handshake(intf); resp.handshake(intf); init.clk (clock); resp.clk (clock); // Open a trace file sc_trace_file *fp; fp = sc_create_vcd_trace_file("wave"); sc_trace(fp, intf, "intf"); sc_start(); sc_start(600, SC_NS); sc_close_vcd_trace_file(fp); cout << "Simulation finished @ " << sc_time_stamp() << endl; sc_stop(); return 0; };
  23. Hello, Sir, qinhailiang! Did you solve this issue? I have the same one.
  24. Tech savvy

    UVM

    What is VIP skeleton? can anyone please explain by an example or sample?
  25. vasu_c

    tlm_fifo nb_peek

    Hi, Thanks for the response. In lined is the test case that fails to compile. #include "tlm" #include "systemc.h" class slave : public sc_module { public: sc_port<tlm::tlm_fifo_get_if<int> > target_port; SC_HAS_PROCESS(slave); slave(sc_module_name nm) : sc_module(nm) { SC_THREAD(run); } void run() { for(int a = 0 ; a < 20 ; a++) { int b; target_port->nb_peek(b); std::cout << b << " "; } } }; Errors: test.cpp: In member function 'void slave::run()': test.cpp:17:17: error: request for member 'nb_peek' is ambiguous target_port->nb_peek(b); ^ In file included from systemc/install/systemc-2.3.2/linux_x86_64/include/tlm_core/tlm_1/tlm_req_rsp/tlm_channels/tlm_fifo/tlm_fifo.h:39:0, from systemc/install/systemc-2.3.2/linux_x86_64/include/tlm_core/tlm_1/tlm_analysis/tlm_analysis_fifo.h:23, from systemc/install/systemc-2.3.2/linux_x86_64/include/tlm_core/tlm_1/tlm_analysis/tlm_analysis.h:29, from systemc/install/systemc-2.3.2/linux_x86_64/include/tlm:26, from test.cpp:1: systemc/install/systemc-2.3.2/linux_x86_64/include/tlm_core/tlm_1/tlm_req_rsp/tlm_1_interfaces/tlm_fifo_ifs.h:54:16: note: candidates are: bool tlm::tlm_fifo_debug_if<T>::nb_peek(T&, int) const [with T = int] virtual bool nb_peek( T & , int n ) const = 0; ^ In file included from systemc/install/systemc-2.3.2/linux_x86_64/include/tlm_core/tlm_1/tlm_req_rsp/tlm_1_interfaces/tlm_fifo_ifs.h:28:0, from systemc/install/systemc-2.3.2/linux_x86_64/include/tlm_core/tlm_1/tlm_req_rsp/tlm_channels/tlm_fifo/tlm_fifo.h:39, from systemc/install/systemc-2.3.2/linux_x86_64/include/tlm_core/tlm_1/tlm_analysis/tlm_analysis_fifo.h:23, from systemc/install/systemc-2.3.2/linux_x86_64/include/tlm_core/tlm_1/tlm_analysis/tlm_analysis.h:29, from systemc/install/systemc-2.3.2/linux_x86_64/include/tlm:26, from test.cpp:1: systemc/install/systemc-2.3.2/linux_x86_64/include/tlm_core/tlm_1/tlm_req_rsp/tlm_1_interfaces/tlm_core_ifs.h:116:16: note: bool tlm::tlm_nonblocking_peek_if<T>::nb_peek(T&) const [with T = int] virtual bool nb_peek( T &t ) const = 0;
  26. maehne

    tlm_fifo nb_peek

    Thanks for providing this feedback on the SystemC PoC implementation! It would help if you could share some more details about the exact error messages as well as a minimal self-contained example exposing the problem you are observing. Then, we may discuss the issue more seriously.
  27. UVM 1.2 manual documents that uvm_reg_map can be added as sub-map to multiple address maps (captured as below), But in the implementation, it is just throwing error when same map is added to 2nd map as submap. Is there any alternate solution recommended by UVM for this? // Cannot have more than one parent (currently) if (parent_map != null) begin `uvm_error("RegModel", {"Map '", child_map.get_full_name(), "' is already a child of map '", parent_map.get_full_name(), "'. Cannot also be a child of map '", get_full_name(), "'"}) return; end Manual Statement : An address map may be added to multiple address maps if it is accessible from multiple physical interfaces. An address map may only be added to an address map in the grandparent block of the address submap.
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