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  2. Constraints

    a rand var which divides by 7 and 17 can be divided by 7*17 (since both are prime). so the constraint should be as simple as x % (7*17) == 0 //uwe
  3. Last week
  4. Constraints

    How to write a constraint for random variable which is divisible by 7 && 17
  5. It is possible to set RNG seed for each process in a module (always_.., initial, etc.). To do this it is necessary to have a process handler: module dut(); int i; process P1; initial begin P1 = process::self(); #2; i = $urandom_range(0, 500); $display("The value of i is %1d", i); end endmodule // dut Now you can set seed for each process individually: module top_tb; initial begin #1; // Wait process handlers to be created // Set seeds dut_a.P1.srandom($urandom); dut_b.P1.srandom($urandom); dut_c.P1.srandom($urandom); end dut dut_a(); dut dut_b(); dut dut_c(); endmodule
  6. Hi Ralph, Believe me, I have tried all the possible combinations with the same result. :) Regarding the libraries, I have installed the systemc using homebrew package manager and then I compiled systemc-ams using the standard macOS compiler (4.2.1 from Xcode). Regards, Américo PS: I guess the fix for this will be to use a linux virtual machine. :) PS2: The exact same code compiles without errors or warnings in Ubuntu 17.04.
  7. Hello, We received an IP-XACT 2009 file with an empty model name : <spirit:model> <spirit:views> <spirit:view> <spirit:name>View</spirit:name> <spirit:envIdentifier>EnvId:EnvId:EnvId</spirit:envIdentifier> <spirit:modelName></spirit:modelName> </spirit:view> </spirit:views> Both IP-XACT 2009 and 2014 section 1.5.4.5.1 explain how to manage such situation for mandatory element, but do not for optional elements. For this particular situation (modelName), we consider this element as it is not present. But I didn't investigate if this is always the correct answer for all element in the schemas, particularly if the empty element has XML attributes. Do we need to raise this point to the Accellera consortium for next IP-XACT release ? Regards, Grégoire Avot.
  8. In examining the early adopter specification, I'm noticing that the 'extend' syntax will accept a 'struct' type_identifier, but it does not accept a 'struct_declaration' in general--which could include the struct_qualifiers "buffer", "stream", "state", or "resource". This would mean that a buffer declared as: buffer data_buff_s { rand data_s my_data; }; would be extended as extend struct data_buff_s { rand int[0..3] my_id; }; not extend buffer data_buff_s { rand int[0..3] my_id; }; correct?
  9. grammar corrections

    Section B.10 -- Is the syntax for "expression_constraint_item" correct (line 15 of page 202)? This appears to state that an implicand_constraint_item is required to accompany an expression...
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  11. Welcome to the age of deep learning, where spam looks like a real post but links to a diet website?! Don't click the link!
  12. Thanks Phillipp and Ralph, Appreciate the response and apologize for the delay but This may confuse users. Especially See This. If I change the the type of vectors from sc_bv to sc_lv, I would not expect any changes in the behaviour (unless 'Z' or 'X' appear in the model).
  13. I suppose the committee has already have noted these typos, but here goes. Section 11.7.7, p.83, line 9: "and domain_B is 1" should read "or domain_B is 0" to be consistent with the constraint on line 20. Section 13.3.3, pp. 137-138. Actions a2 and a3 are present in Example 105, but not Example 104. Actually, it is very difficult to follow the explanation on page 123 by looking at Example 104. Section 14.6.1, p.160. Lines 5 and 26 contain this line ignore burst_type ? (burst_len < 2) : 1; The "1" next to the semicolon should probably be a zero to match the stated ignore buckets. Similar code appears on p.161. Section 15.2.3, p.173, lines 19-20. The sentence "Action reg2axi_top_x specifies all instances of axi_write_action need to be instances of axi_write_action_x4, which supersedes the override in reg2axi_top" does not correspond to anything in Examples 140 and 141, and may need to be deleted.
  14. Purpose of modifiedWriteValue = oneToSet?

    For all of the bitwise modifiedWrite functions (oneToClear, oneToSet, oneToToggle, zeroToClear, zeroToSet, zeroToToggle) the specified bit write value changes the target bit and the opposite bit write value leaves the target bit unchanged. This provides atomic write access to modify a single bit within a field within a single write transaction. For fields with normal write behavior the write replaces the target field value with the write value. This feature was inherited and expanded from Accellera SystemRDL 1.0 standard which at least has equations for the few bitwise write behaviors it supports. The IEEE 1800.2-2017 UVM standard inherited this feature from IP-XACT and has a slightly better description. We'll make sure that the next version of the standard specifies more completely the behavior of modifiedWrite.
  15. Purpose of modifiedWriteValue = oneToSet?

    Hi Michael, My understand is that oneToSet also means that writing a 0 has no effect. Best regards, Erwin
  16. IEEE Std 1685-2014 includes this: I don't understand the purpose of oneToSet. It seems to describe the basic functionality that any read/write field should have, without any modifications. In other words, when I receive this code from an IP vendor of mine: I don't understand how that is any different from simply this: In both cases, when I write a 1 to this field, the field becomes 1. Can someone clarify what purpose the oneToSet modifiedWriteValue serves? Thank you.
  17. TLM 1.0 => TLM 2.0

    TLM1.0 was just a methodology and not a standard like TLM2.0. So, either modify the existing model or write a transactor in which case it would be specific to the your TLM1.0 interface.
  18. UVM Override V/s Simulator Compile/Elab

    Yes it should work. It skipped from my mind. Thanks a lot :)
  19. UVM Override V/s Simulator Compile/Elab

    You cannot reference to "abc" on handle of my_transaction type. Try using $cast as below. begin extended_transaction etx; if($cast(etx,tx)) $display("DEBUG_CODE: IN driver abc = %d",etx.abc); end
  20. Hello, I've run into a rather obscure scenario. I have multiple parallel sequences which push items to the same sequencer. These sequence will call lock and unlock before starting a small number of transactions. Here is what I observe. sequence A calls lock(this) and is unblocked at time t sequence C+D call lock at time t+1 sequence A calls unlock(this) once it is finished at time t+2 At time t+3, both sequences C and D appear to be unblocked (lock granted) in the same simulation cycle. Here is a print out... unblocked port_id: 2, @ 5394166 ps unblocked port_id: 1, @ 5394166 ps After this, at least one of the unblocked sequences (I only stepped through sequence C) have their "wait_for_grant" not complete. Hence, "start_item" is perpetually blocked (while the sequence has the sequencer lock) and the sequencer does not grant any more sequences access to the driver. Here is some sample code. forked threads... parallel sequence_a.start(sqr) parallel sequence_b.start(sqr) parallel sequence_c.start(sqr) join... sequence_[A/B/C] body() sqr.lock(this). [all the typical transaction item code] start_item(transaction); <--- does not return/unblock. wait_for_grant() not returning. ... finish_item(transaction); endtask At this point I am resorting to writing my own semaphore to control access to the agent. However, any deep insight or pointers are highly appreciated. I am using UVM 1.2 and the latest Cadence tools. Thanks, Borna I also found this which sounds similar! The closest replication of this issue on the forums:
  21. Hello, Are the header files listed in Annex C available for download anywhere? Thanks, Brandon
  22. Converting sc_signal<T1> to sc_signal<T2>

    Yes, but in most cases copy is not created , but used as rvalue in computations. Most likely end user can do something like: auto val = some_signal.read(); that also creates a copy anyway. Great idea. Unfortunately it is not possible to apply it for hierarchical bindings, that are also quite common case where type conversion happes, i.e. when you bind sc_in<T1> to sc_in<T2>
  23. Converting sc_signal<T1> to sc_signal<T2>

    Any eventual copy returned from read() by value will never be optimized away, as the source location continues to exist in the signal. The simplest solution is to change your signal converter as follows (untested): template <typename Treal, typename Tcasted> class signal_interface_converter : public sc_core::sc_signal<Treal> , public sc_core::sc_signal_in_if<Tcasted> // only read allowed { typedef sc_core::sc_signal<Treal> real_type; public: explicit signal_interface_converter(const char* nm) : real_type(nm), casted_val() {} const Tcasted &read() const override { return casted_val; } private: void update() override { real_type::update(); casted_val = static_cast<Tcasted>(real_type::read()); ] Tcasted casted_val; }; So the idea is basically to leverage the update phase to update the casted value. If the above doesn't work due to read() overloads based on the return type only, you may need to wrap it differently to separate the two conflicting interfaces (e.g. by using an internal signal with an overridden update() function, triggering the update of the casted value in the converter). Hope that helps, Philipp
  24. Execution Trace Generation

    Hello @R.Adiga, I have developed something similar you can have a look here: https://github.com/AmeyaVS/trace-ninja (Still under development but basic functionality implemented for getting traces). If you are developing on Linux I would suggest of having a look here: https://github.com/namhyung/uftrace , which offers much better tracing capabilities and lower latencies. Both the methodologies are dependent on using GCC toolchain for building the SystemC library. The only advantage you get on using my project is that it would work under Cygwin/Windows with GCC compiler (Not tested under MinGW). Regards, Ameya Vikram Singh
  25. Hi Folks, Interestingly today making some tweaks I faced a scenario with overrides. Suppose I add some variables in the extended class which are not present in the base class. Then I called the uvm_set_type_override from my top test. Interestingly I wanted to access those newly added variables in final_phase of some component , but during the simulator compile/elaboration phase it fails since the overrides are active during Simulation run-UVM_BUILD_PHASE. So my question is , if someone using some legacy code and wanted to update the stuff without re-writing again/or major changes , extended from base, then only overrides possible are those that will be active during simulation run , for an example , setting default sequence to driver with override. So there is no way we could leverage it. I am wandering , if TLM-GP extensions implementation may provide my some idea to do this. Any suggestions ??? If needed a code to see I saved the stuff http://www.edaplayground.com/x/2Ltr Line 156 is point of interest
  26. Microsoft Visual Studio Community 2015

    What exactly does not work for you? Did you tried 2.3.2 draft? http://www.accellera.org/downloads/drafts-review
  27. Microsoft Visual Studio Community 2015

    Hi installed the latest version 2.3.1 and I have an error saying gets is not member of std. I have commented that line still does not work.
  28. Converting sc_signal<T1> to sc_signal<T2>

    Hi Ralph, Compiler should optimize a copy when possible. So it should not be a performance bottleneck. Its not my problem, but it is a problem in general. A write-through to temp_val will be a SC_METHOD sensitive to value_change_event(). This will be a performance problem when a lot of traffic goes through such a converter Yes, this is another issue.
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