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  1. Today
  2. As Philipp says, there is now a rudimentary 'implementation' within the CCI code, but please be in touch with me @greensocs, if you would like to use our implementation which supports various configuration files etc. Cheers Mark.
  3. SystemC-AMS vs RNM

    When it comes to modelling, you open the door to so many things. There are more options nowadays and It really depends on more things like: what effects/features you want your model to show? Is it a model for verification? is it for IP design? Is it a model you want to deliver to your customer? I don't believe there is one tool for everything. As usual, you need the right tool for the right task. Finally, it depends also on one modelling skills. While is common to talk about design and verification skills. It is also common to forget that modelling requires special skill-sets and understanding. RNM has been for me enough good on many occasions. However, depending on what you want to model it might not be anymore the right tool out there. Can you give an example of an IP you are trying to model and what kind of effects you want to model?
  4. I just saw, that it looks like you instantiate the modules statically. You may run into the OS stack size limitation. Allocate the modules/vectors dynamically (using new) may solves the problem (or at least increases the possible size). May you can try similiar like this (not checked): sc_vector< sca_eln::sca_node >* c_vec; //nodes beteen resistors sc_vector<sca_eln::sca_r>* rs_vec; SC_CTOR(rmatnn): p("p"),n("n") // { c_vec=new sc_vector< sca_eln::sca_node >("c_vec", N ); rs_vec=new sc_vector<sca_eln::sca_r>("rs_vec", N ); ... }; what are the shell messages before the segfault?
  5. Yesterday
  6. CCI git repository

    Hi Sumit, The repo is still there, but it is private to the Accellera CCIWG. If you are an Accellera member, you can request access separately. (For GreenSocs-specific parts, you need to contact GreenSocs, of course. The Accellera proof-of-concept implementation doesn't depend on GreenSocs anymore). Greetings from Duisburg, Philipp
  7. Problem building CCI using CLang 6.0

    Thanks for reporting, Eyck! I have submitted the suggested fix to the WG for review.
  8. I am looking for the updated source code for greensocs CCI implementation. Earlier it was at https://github.com/OSCI-WG/cci.git but now I am not able to find it Anybody knows from where I can get this ? Thanks Sumit
  9. I get same problem for same value of N with system of 32GB RAM and 8GB Ram
  10. Timing Annotation

    Thanks @Eyck I want to understand clearly in figure 26 above, The initiator sends to target with timing annotation is 10ns, when targets received the request, it is delay 10ns (timing annotation) then the target begin handing request I understand is right or wrong????
  11. Last week
  12. There is no real limitation except the available memory. Each resistor is a SystemC module which allocates some memory due the sc_module members. I guess SystemC and SystemC AMS does not check always, that memory could be allocated - thus you get the segfault. You can try a computer with more memory or try to setup the equation manually- for a resistive network this should be some lines of c code only - if you have inductors or capacitors you can use the state space or Ltf objects.
  13. Hello there, I'm building a system that includes a large number of resistors. I used sc_vector of elements and nodes, as I increase the number of resistors I get segmentation error. The below example is a simpler form of my code that also gives the same error In the code below if I use small value of N: ( N=10000): I get the right result but for N=1048576: //(large N) I get: Segmentation fault (core dumped) ------------------------------------------------------resistors in series module---------------- // p- r0-r1-r2-r3...rN -n static const int N=1048576; sca_eln::sca_terminal n; sca_eln::sca_terminal p; sc_vector< sca_eln::sca_node > c_vec{"c_vec", N }; //nodes beteen resistors sc_vector<sca_eln::sca_r> rs_vec{"rs_vec", N }; SC_CTOR(rmatnn): p("p"),n("n") // { rs_vec[0].p(p); //connect p port of first resistor to main p port rs_vec[0].n(c_vec[0]); //connect n port of first resistor to nod 0 rs_vec[0 ].value=10; for (int i = 1; i < N-1; i++) { rs_vec[i ].p(c_vec[i-1]); rs_vec[i ].n(c_vec[i]); rs_vec[i ].value=10; } rs_vec[N-1 ].p(c_vec[N-2]); rs_vec[N-1 ].n(n); rs_vec[N-1 ].value=10; } }; Is there any limitations on the number of modules we use for the simulation?? Thanks in advance
  14. Timing Annotation

    Whenever you call a generic protocoll function lile b_transport or nb_transport you supply an sc_time argument as reference so it can changed be the callee. This delay argument is the offset of the begin (when calling the function) or to the end (after the function returns) of this transaction to the current simulation time point. This is called timing annotation... Best regards
  15. Well, usually this describes the simulation timing behavior of a system. Approximately-timed models breakdown communication protocols into the subsquent phases with attached time points and durations. The components of a system adhere to a common or global time base - they execute in sync. In loosly-timed models part of the system are allowed to stick to their own time base which might deviate from the global time base by a given amount (the quantum). Communication transactions a handled as a single transaction with annoteted time points so that the components can react acccordingly. As a simple example let's have a look at an instruction set simulator (ISS). In AT mode it would execute one machine instruction, do all the bus transactions at the correct points in time (related to the global time base). Thus interactions in the system (triggering interrupts, writing GPIO pins etc.) are fairly correct from a timing point of few. But it inccurs quite some overhead as the execution (in the simulation) switches very often from the model to kernel and back (so called context switches). In LT mode the ISS is allowed to execute a whole bunch of instructions without returning the control to the simulation kernel. Usuallay this implies that communication transaction are executed in a blocking fashion without wait() calls. To be able to run-ahead and still have time passing the ISS has to maintain a local time base (the local quantum). In the case of simple memory read and writes this has no effect on the entire system but it saves a lot context switches so it boosts the performance. To make sure that the functionality get not sacrificed each interaction with the system carries an annotated delay so that the reciever of the transaction (e.g. a timer) can decide to stop the ISS execution simulation thread and let the rest of the simulation catch up - it breaks the quantum. In practice you will find mostly mixtures of the 2 apporaches but I hope this gives you an idea. Cheers
  16. Could you explain LT ( loosely-timed) and AT(approximately-timed ) thanks
  17. Hi shanh, looking at the SystemC LRM: this is what happens in your example. The event is notified while another event is pending since your 2 threads sleep for the same amount of time. You would need to guard the event notification, use 2 separate events or an event queue similar to tlm_utils::peq_with_cb_and_phase. Best regards
  18. async_request_update() multiple events

    Remember that the SystemC OS thread is completely asynchronous to external threads and processes. Async_request_update() simply says to call update() once at the end of the delta cycle for a single object. So you can get multiple notifications within the same delta and only get one call-back. To keep from losing these you should setup a threadsafe mailbox/queue. Rather than just notify the event, you should also put an entry into the mailbox on each activation. Then your threadsafe update() method can see the multiple requests accurately.
  19. A small example of async_request_event. It only triggers the first event and not the second one? Can anyone please explain why? #include <systemc> #include <unistd.h> #include <thread> using namespace sc_core; class ThreadSafeEventIf : public sc_interface { virtual void notify(sc_time delay = SC_ZERO_TIME) = 0; virtual const sc_event &default_event(void) const = 0; protected: virtual void update(void) = 0; }; class ThreadSafeEvent : public sc_prim_channel, public ThreadSafeEventIf { public: ThreadSafeEvent(const char *name = ""): event(name) {} void notify(sc_time delay = SC_ZERO_TIME) { this->delay = delay; async_request_update(); } const sc_event &default_event(void) const { return event; } protected: virtual void update(void) { event.notify(delay); } sc_event event; sc_time delay; }; SC_MODULE(Foo) { public: SC_CTOR(Foo) { SC_THREAD(main); SC_METHOD(eventTriggered); sensitive << event; dont_initialize(); } private: void main() { usleep(5 * 1000 * 1000); // Just for the example, event is added to pending events during this sleep wait(SC_ZERO_TIME); // Schedule (event is evaluated here) usleep(1 * 1000 * 1000); // Just for the example std::cout << "Done" << std::endl; } void eventTriggered() { std::cout << "Got event" << std::endl; std::cout << "sc_time " << sc_time_stamp() << std::endl; } public: ThreadSafeEvent event; }; void externalHostThread(void *arg, int d) { usleep(1 * 1000 * 1000); // Just for the example Foo* foo = (Foo*)(arg); foo->event.notify(sc_time(d,SC_NS)); std::cout << "Event notified from an external host thread" << std::endl; } int sc_main(int argc, char *argv[]) { Foo foo("foo"); int delay1 = 10; int delay2 = 15; std::thread t1(externalHostThread, &foo, delay1); std::thread t2(externalHostThread, &foo, delay2); sc_start(); t1.join(); t2.join(); return 0; }
  20. Hi. Thank you for you answer ! it help me understand more about systemc ! my question is updated. forcus about system level and high level design. Thanks ! ^^
  21. Hi, maybe I do not get the intent of your question but since SystemC is a C++ class library there is no separation between C++ and SystemC. What usually is separate are functional models and timed models as the latter one introduce a notion of time. As a functional model does not have this notion of time (only of sequence) care has to be taken to integrate a functional model into/with a timed model. Hope that helps
  22. Hi everybody ! I have a one question about SystemC model . Why do model separate part designed by SystemC and C++? Regards, Boyheyt P/s sorry because i'm beginer of systemC so maybe my question not detail. Thank all !
  23. Timing Annotation

    @apfitch can you explain timing annotation ??
  24. Changing the width in sc_bv<W>

    These questions have little to do with SystemC per se, and are really about C++. Templates are all about compile-time elaboration and template arguments must be compile-time computable. If you use C++11 or later, then various forms of constexpr functions may be available, but they are still compile-time issues. You could of course use sc_bv_base and its constructors, but keep in mind that modules, ports, and other "hardware" constructs are not allowed to be modified after end_of_elaboration. KEY POINT: To be an effective SystemC designer, you MUST be proficient at C++. Minimal C++ is NOT enough. Knowledge of C (even expert knowledge) is totally inadequate and in some cases downright harmful. Furthermore, really good SystemC often requires excellent C++ skills. Therefore, before you even consider learning much in SystemC, you really should invest in a solid C++ course. Expert SystemC practitioners take time to continually update their C++ skills. If this does not sound like fun to you, then I would advise choosing a different discipline.
  25. define sc_main in VS 2017

    @Aaron0127 try this : Project->property->Linker->All Option->Subsystem : Console (/SUBSYSTEM:CONSOLE) Regards, Hook
  26. Changing the width in sc_bv<W>

    In many cases , I cant use "const" I often use : #define or enum{}; you can try : #define WDW_SIZE 2 or enum {WDW_SIZE=2}; Best regards
  27. Hi, when using CCI 0.9.0 with CLang 6.0 I get a compiler error: cci_broker_handle.h:139:42: error: calling 'get_param_handle' with incomplete return type 'cci::cci_param_untyped_handle' return cci_param_typed_handle<T>(get_param_handle(parname)); ^~~~~~~~~~~~~~~~~~~~~~~~~ This can be solved by a #include "cci_cfg/cci_param_typed_handle.h" at line 27 of cci_broker_handle.h. I have no clue how this works when using gcc (and it works :-S) Best regards -Eyck
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