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  2. how to implement delay in systemC?

    No, it will be using event one way or another. Verilog implementation most likely also uses even queue under the hood. It just has a more pretty syntax for it.
  3. Hi all, is there any way to implement the intra assignment delay in systemC without using sc_event()? for example : in verilog we write out = #10 in1 + in2; // intra assignment delay. how would i implement the same in systemC? regards, jatin
  4. How to model a delay line in SystemC

    Hi Roman Popov, is there any way to implement the intra assignment delay without using sc_event()? regards jatin
  5. Yesterday
  6. That is a great news. Will this time add some examples about how to driving clock/reset signal as I ask in this post?
  7. Profiling SystemC using gprof

    Thank you very much!
  8. We are working on releasing an compatibility update rather soon, probably this year.
  9. Hi Aixeta, this is already fixed in the upcoming release of the SCV. Meanwhile you can workaround by casting directly to sc_logic: sc_dt::sc_logic_value_t(this->_get_instance()->get_bit(i))
  10. Hi there, I have an exact same problem with Sephan, when i ran "make' command after do the config the error said like "error: cannot convert 'sc_dt::sc_bv_base::value_type {aka bool}' to 'sc_dt::sc_logic_value_t' in return { this->initialize(); return this->_get_instance()->get_bit(i); } \" I'm using centOS 7 3.10.0-693.5.2.el7.x86_64 and GCC Version gcc version 4.8.5 20150623 (Red Hat 4.8.5-16) (GCC) The scv that i used was "scv-2.0.0a-20161019 " Do you have any suggestion? here the full output making all in sis make[4]: Entering directory `/usr/local/scv-2.0.0/objdir/src/cudd/2.3.0/sis' make[4]: Nothing to be done for `all'. make[4]: Leaving directory `/usr/local/scv-2.0.0/objdir/src/cudd/2.3.0/sis' make[4]: Entering directory `/usr/local/scv-2.0.0/objdir/src/cudd/2.3.0' make[4]: Nothing to be done for `all-am'. make[4]: Leaving directory `/usr/local/scv-2.0.0/objdir/src/cudd/2.3.0' make[3]: Leaving directory `/usr/local/scv-2.0.0/objdir/src/cudd/2.3.0' make[3]: Entering directory `/usr/local/scv-2.0.0/objdir/src/cudd' make[3]: Nothing to be done for `all-am'. make[3]: Leaving directory `/usr/local/scv-2.0.0/objdir/src/cudd' make[2]: Leaving directory `/usr/local/scv-2.0.0/objdir/src/cudd' Making all in scv make[2]: Entering directory `/usr/local/scv-2.0.0/objdir/src/scv' /bin/sh ../../libtool --tag=CXX --mode=compile g++ -DHAVE_CONFIG_H -I. -I../../../src/scv -I../../config -I../../src -I../../../src -I../../../src/cudd/2.3.0/cudd -I../../../src/cudd/2.3.0/obj -I../../../src/cudd/2.3.0/util -I../../../src/cudd/2.3.0/mtr -I../../../src/cudd/2.3.0/st -I/usr/local/systemc-2.3.2/include -Wall -Wformat -O2 -g -MT libscv_la-scv_constraint.lo -MD -MP -MF .deps/libscv_la-scv_constraint.Tpo -c -o libscv_la-scv_constraint.lo `test -f 'scv_constraint.cpp' || echo '../../../src/scv/'`scv_constraint.cpp libtool: compile: g++ -DHAVE_CONFIG_H -I. -I../../../src/scv -I../../config -I../../src -I../../../src -I../../../src/cudd/2.3.0/cudd -I../../../src/cudd/2.3.0/obj -I../../../src/cudd/2.3.0/util -I../../../src/cudd/2.3.0/mtr -I../../../src/cudd/2.3.0/st -I/usr/local/systemc-2.3.2/include -Wall -Wformat -O2 -g -MT libscv_la-scv_constraint.lo -MD -MP -MF .deps/libscv_la-scv_constraint.Tpo -c ../../../src/scv/scv_constraint.cpp -fPIC -DPIC -o .libs/libscv_la-scv_constraint.o In file included from ../../../src/scv/scv_introspection.h:625:0, from ../../../src/scv/scv_constraint.h:65, from ../../../src/scv/scv_constraint.cpp:43: ../../../src/scv/_scv_introspection.h: In member function 'sc_dt::sc_logic_value_t scv_extensions<sc_dt::sc_bv_base>::get_bit(int) const': ../../../src/scv/_scv_introspection.h:552:66: error: cannot convert 'sc_dt::sc_bv_base::value_type {aka bool}' to 'sc_dt::sc_logic_value_t' in return { this->initialize(); return this->_get_instance()->get_bit(i); } \ ^ ../../../src/scv/_scv_introspection.h:573:3: note: in expansion of macro '_SCV_BIT_BASE_INTERFACE' _SCV_BIT_BASE_INTERFACE(type_name) \ ^ ../../../src/scv/_scv_introspection.h:577:1: note: in expansion of macro '_SCV_TAG_FINAL_COMPONENT' _SCV_TAG_FINAL_COMPONENT(sc_bv_base); ^ make[2]: *** [libscv_la-scv_constraint.lo] Error 1 make[2]: Leaving directory `/usr/local/scv-2.0.0/objdir/src/scv' make[1]: *** [all-recursive] Error 1 make[1]: Leaving directory `/usr/local/scv-2.0.0/objdir/src' make: *** [all-recursive] Error 1
  11. Profiling SystemC using gprof

    https://stackoverflow.com/questions/23407635/append-compile-flags-to-cflags-and-cxxflags-while-configuration-make
  12. Hello, I am using SystemC 2.3.0. I am wondering how I can profile the SystemC library. I found we can use options like "--enable-debug" and "--disable-optimize" for debugging and optimization, respectively, but I was unable to find such an option to enable profiling. I need to use gprof and pass "-pg" options when building SystemC. Any help is greatly appreciated! Thank you in advance.
  13. Last week
  14. buildCommand for c/c++ object file

    That's because -c and -o are redundant in this particular case of the g++ command. The target is already given by <ipxact:targetname> while the source file is given by <ipxact:file>
  15. Delta Cycle and concurrency

    Thanks for the suggestion, Raph. Will have a look. Jocelyn
  16. Delta Cycle and concurrency

    Hi. Maybe you should have a look at SystemC AMS. It offers the TDF (timed data flow) model of computation. It follows the data flow concept, i.e. you have a cluster of blocks; the solver defines an order of evaluation of each block; and in every time step, the blocks (or modules) are evaluated in that order. The output of one block is immediately visible at the input of the following block. Greetings Ralph
  17. Delta Cycle and concurrency

    The consumer should never block in my case. Reading twice a shared variable which has only been written once should not block the reader...
  18. Delta Cycle and concurrency

    Ok, thanks. This is indeed what i suspected. Exactly. In fact, this is the kind of solution i'm investigating. I'm starting from a compiler internal representation of the application as a graph of FSMs connected via shared variables. Each FSM is implemented as a SystemC module. The idea is to extract from the graph the chain of dependencies - i.e. which module(s) read (resp. write) each variable - and to insert delta wait(s) at the right place(s). In the example above, this would involve rewriting B as void B::my_thread() { while ( 1 ) { wait(h.posedge_event()); wait(SC_ZERO_CYCLE); if ( v == 1 ) xxx; ... } }; Cyclic dependencies can be detected statically (as loops in the graph) and the corresponding programs rejected i guess.
  19. Delta Cycle and concurrency

    If your issue is that you don't like to have two variables: data and event, you can create a convenient class like sc_signal, that will pack data end event together. Essentially it will be sc_fifo with immediate notification and capacity == 1. If consumer reads from empty fifo it will be blocked until producer writes into fifo. With immediate notification it will be resumed in the same delta cycle as producer writes into fifo.
  20. Delta Cycle and concurrency

    Ok, understood. Yes, the only way to execute this in a single delta cycle is to enforce execution order using events with immediate notification. It is impossible to implement it in other way in C++. What you want is a “SystemC-language-aware” compiler. Such a compiler will need to understand a semantics of processes and create a static schedule: such as a producer processes are always executed before consumer processes. Static scheduling is not always possible, because some processes can have cyclic data dependencies. So as you’ve said, sometimes it will need to resolve <<undeterminacy by iterating until a fix-point is reached>> But since SystemC is just a library, it can't guess what your processes code is doing (because C++ has no code reflection capabilities).
  21. Delta Cycle and concurrency

    Hi Roman, thanks for your feedback. Instantaneous broadcast - also called "perfect synchrony" - means that any update performed to a shared value by a component (a module in our case) will be viewed immediately by other components (and not after n delta cycles, as for sc_signals). Here's a typical example, with two modules : - module A waits for (global) event H (a clock typically) and, when received, set shared variable v to 1 - module B also waits for H but when received only performs action xxx if v=1 (in StateChart, this is called a guarded transition) void A::my_thread() { ... while ( 1 ) { ... wait(h.posedge_event()); v = 1; ... } }; void B::my_thread() { while ( 1 ) { wait(h.posedge_event()); if ( v == 1 ) xxx; ... } }; As explained by Alan, the above implementation does not correspond to the behavior suggested above : - if v is implemented by using a sc_signal, then v only takes value 1 at time t+delta (if H occurs at time t), and hence "too late" for B - if v is implemented as a "regular" shared variable, then the behavior becomes non-deterministic (whether B "sees" v=1 depends on the order at which the scheduler runs the corresponding threads, which is un-predictable). Currently, I don't see a solution other than enforcing execution order using sc_events (as suggested by Alan). But this seriously complicates the translation from formalisms supporting the SB hypothesis to SystemC. I was just wondering if i was missing sth about SystemC semantics or whether this was simply not possible.. Jocelyn
  22. Delta Cycle and concurrency

    Can you please elaborate what do you mean by instantaneous broadcast for those who are not familiar with named formalisms? Some small example will be the best.
  23. Delta Cycle and concurrency

    Hi, Sorry for resurrecting this post but it addresses an issue i'm currently facing. Does this mean that it is not possible to implement instantaneous broadcast (as used in StateCharts or synchronous reactive models of computation for ex.) in SystemC ? With the latters, the undeterminacy is resolved by iterating until a fix-point is reached so that the final values of shared variables do not depend on the order of (micro)-steps ? Jocelyn
  24. Thanks for the help. I did some digging too and I also thought it is becaused by the clock events. So I tried to use the set_timeout on that example which should finished in 100 NS. When I set the timeout to 30 NS, it killed the simulation at 30 NS as expected. But when I set it to 200 NS, the simulation will not finish. I haven't figure out why.
  25. Hello @enchanter, After looking into the sources of the UVM-SystemC draft release available here. In the following file under: src/uvmsc/base/uvm_root.cpp, line number 150. Internally the UVM-SystemC class calls the sc_start() function without any parameter to actually kick start the SystemC simulation. Which executes the simulation till events are generated and queued, in your case with clocks the events would always be generated. You could create your own function which reproduces the same behavior in the run_test() method of the uvm_root class, or better would be to extend the uvm_root class to suite your needs. Here is the code snippet from the UVM-SytemC sources: // File: src/uvmsc/base/uvm_root.cpp // Line number: 127 void uvm_root::run_test( const std::string& test_name ) { //disable SystemC messages sc_core::sc_report_handler::set_actions("/OSCI/SystemC", sc_core::SC_DO_NOTHING); // check and register test object m_register_test(test_name); // start objection mechanism fired as spawned process sc_process_handle m_init_objections_proc = sc_spawn(sc_bind(&uvm_objection::m_init_objections), "m_init_objections_proc"); uvm_phase::m_register_phases(); phases_registered = true; // call build and connect phase uvm_phase::m_prerun_phases(); // start simulation (of run-phases) here. try { ///////////////////////////////// sc_core::sc_start(); //<<<<<<< Run simulation forever or until events exists. } //////////////////////////////// catch( const std::exception& e ) { std::cerr << e.what() << std::endl; exit(1); // TODO exit program with error code? } // TODO: move post-run phases to here? Currently they are part of the simulation if (m_finish_on_completion) sc_core::sc_stop(); } Hope this helps. Thanks and Regards, Ameya Vikram Singh
  26. For UVM, it should not start the simulation by directly call sc_start() and sc_stop().
  27. I played with scoreboard/basic example from uvm-systemc package, it finished simulation automatically: But when I try to add clock signal to the DUT and sc_main as below: dut.h #ifndef DUT_H_ #define DUT_H_ #include <systemc> class dut : public sc_core::sc_module { public: sc_core::sc_in<int> in; sc_core::sc_in<bool> clk; sc_core::sc_out<int> out; void func() { int val; val = in.read(); std::cout << sc_core::sc_time_stamp() << ": " << name() << " received value " << val << std::endl; std::cout << sc_core::sc_time_stamp() << ": " << name() << " send value " << val+1 << std::endl; out.write(val+1); } SC_CTOR(dut) : in("in"), out("out") { SC_METHOD(func); sensitive << clk.pos(); } }; #endif /* DUT_H_ */ sc_main.cpp #include <systemc> #include <uvm> #include "testbench.h" #include "dut.h" #include "vip_if.h" int sc_main(int, char*[]) { // instantiate the DUT sc_core::sc_time CLK_PERIOD(10, sc_core::SC_NS); sc_core::sc_clock clk("clk", CLK_PERIOD, 0.5); dut* my_dut = new dut("my_dut"); testbench* tb = new testbench("tb"); //uvm_config_db_options::turn_on_tracing(); vip_if* dut_if_in = new vip_if(); vip_if* dut_if_out = new vip_if(); uvm::uvm_config_db<vip_if*>::set(0, "tb.agent1.*", "vif", dut_if_in); uvm::uvm_config_db<vip_if*>::set(0, "tb.agent2.*", "vif", dut_if_out); my_dut->clk(clk); my_dut->in(dut_if_in->sig_data); my_dut->out(dut_if_out->sig_data); uvm::run_test(); return 0; } The simulation will not stop and I have to kill the process. scoreboard_basic.tar.gz2
  28. Hi. This seems to be related to SystemC in general and not to UVM. sc_start() - without argument - starts the simulation until there is no activity anymore. No activity means no more events in the event queue. sc_clock generates new events all the time because the value changes independent from everything else in your design. As a result, the event queue will never be empty and the simulation never stops. (For completemess: the simulation ends as well when the maximum time is reached, i.e. the maximum time value that can be represented by sc_time). Normally, there are two ways to stop simulation, either by calling sc_start with a argument or by calling sc_stop. The first has been mentioned already by AmeyaVS. It runs the simulation for the given time and stops. The second can be done for instance from a testbench thread, e.g. from a sequencer when all sequences are done. Greetings Ralph
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