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  1. Past hour
  2. Khushi

    Array of ports

    Thanks Eyck. Appreciated your quick help. Thanks again, Khushi
  3. Today
  4. Hi, there is no way to do this easily. Actually you have 32 output ports and 1 input port. So you need to connect the output ports to 32 bool signals and the input port to a uint32_t signal as well and make a SC_METHOD sensitive to all of the 32 bool signals. Within that method you iterate over the 32 bool signals and collect them into a 32bit value. BTW, having a POD array of ports is not preferable, I would use 'sc_core::sc_vector<sc_core::sc_out<bool>> out;'. This way you gain several things: the ports are initialized with a name based on the sc_vector instance name and you can bind a vector of ports to a vector of signals with a single line statement. Best regards
  5. Hi Guys I have a scenario where I have to connect sc_in<uint32_t> in_port to an sc_out<bool> out[32] out_ports. i.e. the xth bit in in_port need to be connected to out[x] Is there a way to connect these ? Thanks Khushi
  6. HoltRead

    Direct Digital Synthesis

    Hi.... one of the acronyms you may hear thrown around is DDS which stands for Direct Digital Synthesis. DDS can be as simple as taking a digital value — a collection of ones and zeroes — and processing it through a Digital to Analog Converter (DAC) circuit. For example, if the digital source is the output of a counter that counts up to a maximum value and resets then the output of the DAC would be a ramp (analog signal) that increases in voltage until it resets back to its starting voltage.
  7. mastrick

    RAL Backdoor write

    I believe the UVM intent of is to associate the (whole) signal "IP.REG.regout" with the 16 bits starting at offset 16 of the data in the reg model. The start and offset do not affect the signal, and so you do need to provide the bit range as you show to associate a slice of the signal with a slice of the internal data. I agree the documentation does not make that clear, and I have filed a Mantis to improve that documentation.
  8. Hi , We are trying to do backdoor one of the register in our RAL and set hdl path using add_hdl_path_slice fucntion. Will take similar example here. say we have 32 bit REG1. REG1 has two fields F1 and F2 each of 16 bits. We have set below HDL path : REG1.add_hdl_path_slice("IP.REG.regout", 0,16); REG1.add_hdl_path_slice("IP.REG.regout", 16,16); When we write through REG1.poke and read back , we see only value deposited by last slice. If we deposit value 0x12345678, while reading back , it returns value 0x1234 only. Looks like it overrides value written by previous slice. Question is it necessary to provide bit range in first argument of add_hdl_path_slice ? Or UVM will take care of that ? If we set below path as add_hdl_path_slice , then it works fine and returns correct value 0x12345678. REG1.add_hdl_path_slice("IP.REG.regout[15:0]", 0,16); REG1.add_hdl_path_slice("IP.REG.regout[31:16]", 16,16);
  9. TRANG

    Process sensitivity with sc_vector

    I think if use pointer, my code faster and save memory . my project: ///APM.h class APM: public sc_module { public: sc_in<bool> clkAPM; sc_in<bool> *IFA[4]; ... ///APM.cpp APM::APM(sc_module_name name) :sc_module(name) // Initializing ,clkAPM("clkAPM") {//{{{ /// Initializing std::ostringstream port_name; for (unsigned int index = 0; index < 4; index++) { port_name.str(""); port_name << "IFA" << index; IFA[index] = new sc_in<bool>(port_name.str().c_str()); sc_assert(IFA[index] != NULL); } SC_METHOD(AMethod); dont_initialize(); sensitive << (*IFA)[0]; ... I know this it old style code. So, I want to use sc_vector. Thanks.
  10. Philipp A Hartmann

    Process sensitivity with sc_vector

    Why do you want to do this?
  11. TRANG

    Process sensitivity with sc_vector

    Thanks @Philipp A Hartmann How to use sc_vector with pointer? sc_vector< sc_in< int> > *in_vec;
  12. Yesterday
  13. jrefice

    UVM events with data.

    Access to the mantis database is restricted to Accellera members. I can tell you that the mantis in question was resolved in the UVM 2017 release, and the bug no longer exists.
  14. Philipp A Hartmann

    Why sc_signal<T>::trace() is deprecated ?

    Hi Roman, This would be something to discuss in the Accellera SystemC LWG (or the IEEE P1666 WG). In practice, most/all commercial simulators provide much more advanced tracing mechanisms already, beyond what the current sc_trace() API allows to support. My guess would be, that this part of the standard is something where it is difficult to reach consensus, as it touches the core distinguishing features of commercial SystemC offerings. Moreover, the sc_trace()-based API is a costly "pull" interface, which effectively loops over all variables at each time step and does a value comparison. This is also pretty inefficient for e.g. signals, which already "know" if they changed. So I think, a plain sc_interface::trace() addition is not sufficient to bring real additional value here. Last, but not least, this function would have to have a default (empty) implementation to not break existing models and would require some extension mechanism to add support for custom types. Greetings from Duisburg, Philipp
  15. Hi all, For debugging purposes it may be useful to add all signals in design to trace file. However, sc_signal::trace() which may allow to do it automatically is deprecated. Why is that? In general I think it will be useful to add trace method to sc_interface, so that all channels that support tracing can implement it. And then it will be possible to implement something like: sc_trace_all(sc_trace_file *tf) // add all objects that support tracing to trace file.
  16. Last week
  17. gchinna

    UVM events with data.

    I don't seem to have access to this link: https://accellera.mantishub.io/view.php?id=5636 Do I need to be a registered member employee to be able to view the issues?
  18. Many thanks Roman. You suggestion works. Thanks again - Khushi
  19. Yes, but direction of binds matters. For example if you want to bind ( in0 -> in1 -> signal ) then you will need to write: in0 ( in1 ); in1 ( signal ); OR in1 ( signal ); in0 ( in1 ); In your examples you bind like this: Ex1: port0 <- port1 -> signal // port0 not binded Ex2: signal <- port0 -> signal // port0 binded to 2 signals I agree that error message in first case is misleading.
  20. Hi Guys Is it possible to connect sc_in<bool> hierarchically to another sc_in<bool> (same for sc_out<bool> as well) ? I tried the attached exmples ex1.cpp Error: (E109) complete binding failed: port not bound: port 'target.target_h.in' (sc_in) ex2.cpp : Error: (E109) complete binding failed: 2 binds exceeds maximum of 1 allowed: port 'target.in_h' (sc_in) Can you please help me ? Thanks Khushi ex1.cpp ex2.cpp
  21. TRANG

    Array when declare port for model

    @David Black @Roman Popov Thank for your info. I'm using systemc 2.3.2.
  22. David Black

    Array when declare port for model

    SC_NAMED is not part of IEEE 1666:2011, but rather a newly introduced (SystemC PoC 2.3.2) convenience macro looking for feedback and possible inclusion in the next version of the standard.
  23. Roman Popov

    Array when declare port for model

    Do you use SystemC 2.3.3? Check RELEASENOTES file.
  24. TRANG

    Array when declare port for model

    I tried above code ,but it's not working , Can you share me docs about "SC_NAMED" ? Thank @Roman Popov
  25. Hi Khushi, If a register value is updated internally by the RTL, then the user has to update the register model by calling the predict method of that register class in order to sync the register model with the RTL values. In such cases, wait for the event that causes the change in register value and then update the RAL model with that value. Ex:- @(event causing the change in value) <register_handle>.predict(value due to that change); Ishanee Agnisys Inc.
  26. TRANG

    Array when declare port for model

    Thank you so much @Roman Popov
  27. Roman Popov

    Array when declare port for model

    This is a very old style. With a modern SystemC you can have the same with sc_vector: //exxe.h class EXXE : public sc_module { public: sc_vector<sc_in<sc_dt::uint64>> SC_NAMED(clock,3); sc_vector<sc_in<bool>> SC_NAMED(input,5); EXXE(sc_module_name); ~EXXE(); } But as David mentioned, before starting learning SystemC you should learn C++ first. Trying to understand SystemC without being proficient with C++ is a waste of time.
  28. TRANG

    Array when declare port for model

    @David Black Thank you so much !! I see some projects . They use code as bellow: //exxe.h class EXXE { public: sc_in<sc_dt::uint64> *clock[3]; sc_in<bool> *input[5]; EXXE(); ~EXXE(); } //exxe.cpp ///Constructor EXXE::EXXE() { std::ostringstream name; for (unsigned int index = 0; index < 5; index++) { name.str(""); name << "input" << index; input[index] = new sc_in<bool>(name.str().c_str()); } for (unsigned int index = 0; index < 3; index++) { name.str(""); name << "clock" << index; clock[index] = new sc_in<sc_dt::uint64>(name.str().c_str()); } } But you said that: "None of your three attempted examples appear correct,...." Are they incorrect? Thank @David Black
  29. Earlier
  30. David Black

    Array when declare port for model

    The proper SystemC notion of a port is very different from VHDL or Verilog. Ports are really a very fancy type of pointer used to direct method calls to channels. Note that channels are not signals or wires. Channels are classes that provide public methods to communicate safely between SystemC processes. The sc_core::sc_int<T> port is actually a partial template specialization for the proper SystemC port, sc_core::sc_port<T>. Ports are always bound to SystemC interfaces. A slightly more complete way of expressing this would be: using namespace sc_core; sc_port< sc_signal_in_if <bool> inA; // Port for connecting to a signal channel capable of communicating a single boolean value. Please note that you don't really initialize ports in the sense of assigning an initial value, because ports do not carry values. You do initialize ports in the sense of C++ construction and subsequent binding of ports to channels. SystemC ports have up to three template parameters (although the interface is normally the only one needed) and normally a single optional constructor argument (the sc_object instance name). If very much of the wording I've chosen above is foreign to you, then you probably don't have enough C++ programming background yet. Before tackling SystemC you need to be proficient at C++ (not C). None of your three attempted examples appear correct, but I infer that you may be interested in a port for communicating five bits over an sc_signal channel. This would be done in SystemC as follows: sc_in<sc_int<5>> inB1; or sc_port< sc_signal_in_if<sc_int<5>>> inB2; Note that the following would not work: sc_in<bool> inC[5]; // Attempt to create an array of 5 ports for 5 different sc_signal<bool> connections This is due to the unfortunate manner that array elements are constructed, and SystemC's requirement that component objects must be constructed with unique instance names. I don't have time to go deeper, andI suggest you either get a good book on SystemC or take a formal class. If you don't have a solid grasp of C++, please be certain to get educated on that as well.
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