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  1. Today
  2. Hi Sumit, I re-checked the LLVM issue and it now refers to C++ CWG issue #7 (http://www.open-std.org/Jtc1/sc22/wg21/docs/cwg_closed.html#7), which clearly describes our situation here and shows that the current implementation of tlm_req_rsp_channel<...> is invalid C++ in SystemC (even though only Clang rejects it so far). Without changing the inheritance pattern, the only fix would be to add "friend" declarations to all (indirect) virtual base classes of tlm_put_get_impl<...>, including sc_interface. This is not an option, so I think the internal implementation of the tlm_req_rsp_channel<...> needs to be refactored to avoid the private virtual inheritance. I have opened an issue in the SystemC Language WG bug tracker for this. Greetings from Duisburg, Philipp
  3. Yesterday
  4. Hi Jrefice Thanks for the guidance. Can you elaborate a little more. I mean what to clone and where. I can try accordingly. Thanks
  5. Last week
  6. Would it be sufficient to clone the original sequence, and execute the clone in parallel on the TLM model's sequencer/driver?
  7. Hello Philipp, Would it be possible to bypass the bug by explicitly deleting the destructor [public : ~mclass() = delete;] if the the chosen c++ standard is at or above c++11 ? It started hurting now. Regards, Sumit
  8. I have a RTL DUT verification platform where I integrated the corresponding TLM model as a reference model. I Now I want to drive the same random sequence to both RTL and TLM and compare the result. I want to drive the sequence independently to both RTL and TLM because either of them can finish earlier so it does not need to wait for other to finish before feeding the next sequence. Can anyone guide me how I can do this. May be if you know some pointer for the same. Thanks
  9. I have a RTL DUT verification platform where I integrated the corresponding TLM model as a reference model. I Now I want to drive the same random sequence to both RTL and TLM and compare the result. I want to drive the sequence independently to both RTL and TLM because either of them can finish earlier so it does not need to wait for other to finish before feeding the next sequence. Can anyone guide me how I can do this. May be if you know some pointer for the same. Thanks
  10. Thank you very much. I will test your propositions and keep you in touch. Chaka
  11. Philipp A Hartmann

    Build error with 2.3.2

    SystemC 2.3.2 has been tested successfully with C++03, C++11, C++14 (and even C++17) with various compilers. As mentioned in this thread, the selected C++ standard needs to match between the library build and the application build. This is enforced by the linker error you see. If you continue to run into these errors, make sure to build the SystemC library with the matching C++ standard selection compared to your application (see INSTALL or cmake/INSTALL_USING_CMAKE how to do that).
  12. katang

    Build error with 2.3.2

    Is there any specific reason to test SystemC with a 15-years old standard? And, not testing if at least the "Hello World" can be built with, as given by the example setup test? I do not want either to hunt down and downgrade my sources updated for the new standard or find out if those strange link errors come from version mismatching or they are my own mistake. I have spent some hours with experimenting, then I returned to 2.3.1.
  13. Looks to me like you are declaring sc_clock objects inside the constructor on the stack, which will then be immediately destroyed at the end of construction. They should be class members. Also, you appear to have the intent of using PHREADs; however, SystemC is not thread-safe unless you take special precautions. I would also suggest you consider using std::unique_ptr<> instead managing pointers yourself. Safety first.
  14. Earlier
  15. Hello all, i really your help. I'm getting an segmentation fault (Erreur de segmentation (core dumped) ) and i do not understand how to fix it. when i do the gdb i git thie one as error. i understand that the error occurred on sc_start and the the problem is with libsystemc-2.3.1.so. i need your help to fix it. Thanks in advance, bellow, tou have my source code. #include <iostream> #include <string> #include <vector> #include "math.h" #define SC_INCLUDE_DYNAMIC_PROCESSES #include "systemc.h" #include "tlm.h" #include "tlm_utils/simple_initiator_socket.h" #include "tlm_utils/simple_target_socket.h" #include "pthread.h" #include "timer_counter_sc.cpp" #include <inttypes.h> #include "genMcu.h" #include "sensors.h" #include "genRadio.h" #include "genbattery.h" #include "alldef.h" using namespace sc_core; using namespace sc_dt; using namespace std; GenMcu* o_genericMcu[numberOfSensorNode]= {NULL}; GenSensor* o_genericSensor[numberOfSensorNode]= {NULL}; Transceiver_hc05* o_genericRadio[numberOfSensorNode]= {NULL}; GenBattery* o_genericBattery[numberOfSensorNode]= {NULL}; SCTimerCounter* o_genericTimer[numberOfSensorNode]= {NULL}; SCTimerCounter* o_genericTimer_rf[numberOfSensorNode]= {NULL}; sc_signal<unsigned int,SC_MANY_WRITERS> sizeDataInRam[numberOfSensorNode]; sc_signal< bool ,SC_MANY_WRITERS> radioINT[numberOfSensorNode]; sc_signal< bool,SC_MANY_WRITERS > sig_radioCS[numberOfSensorNode]; sc_signal< bool ,SC_MANY_WRITERS> mcuInt[numberOfSensorNode]; sc_signal< bool,SC_MANY_WRITERS > sig_allPacketsTransmitted[numberOfSensorNode]; sc_signal<float,SC_MANY_WRITERS> sigMcuHC05[numberOfSensorNode]; sc_core::sc_signal<int,SC_MANY_WRITERS> identSensor_io[numberOfSensorNode]; sc_core::sc_signal<bool,SC_MANY_WRITERS> syncSensorsMcu[numberOfSensorNode]; sc_signal<bool,SC_MANY_WRITERS> paquetToTransmit_io[numberOfSensorNode]; sc_signal< bool,SC_MANY_WRITERS > init_simul_i[numberOfSensorNode]; sc_signal< bool,SC_MANY_WRITERS> commandMode_CMD[numberOfSensorNode]; sc_signal< double,SC_MANY_WRITERS> timeElapsed_mcu[numberOfSensorNode]; sc_signal< double,SC_MANY_WRITERS> timeElapsed_radio[numberOfSensorNode]; sc_signal< char,SC_MANY_WRITERS > batt_mcuState[numberOfSensorNode]; sc_signal<char,SC_MANY_WRITERS> batt_radioState[numberOfSensorNode]; sc_core::sc_signal<float,SC_MANY_WRITERS> sensorData[numberOfSensorNode][fsampling]; std::string s; sc_event ev_activeNode_1; const int indexNode =0; SC_MODULE (emotica) { //sc_in<int> indexNode{"indexNode_emoticaM"}; SC_CTOR(emotica) { int HC05 = HC; int mcuType = MCU_t; int radioType = HC05; int selectSensor[3] = {1,2,4}; sc_time period_clk(period_mcu, SC_SEC); //0.125=1/8 @freq_mcu= 8 sc_clock clk("clk", period_clk, 0.5, SC_ZERO_TIME, true); sc_time period_clk_hc05(period_radio, SC_SEC); // @freq_hc05= 1 megabit/s sc_clock clk_hc05("clk_hc05", period_clk_hc05, 0.5, SC_ZERO_TIME, true); std::stringstream stream; stream << indexNode; stream >> s; paquetToTransmit_io[indexNode] = false; commandMode_CMD[indexNode]= false; o_genericMcu[indexNode] = new GenMcu (("mcu"+s).c_str()); o_genericSensor[indexNode] = new GenSensor (("sensor"+s).c_str(),selectSensor[indexNode]); o_genericRadio[indexNode] = new Transceiver_hc05 (("radio"+s).c_str()); o_genericBattery[indexNode] = new GenBattery (("battery"+s).c_str(), mcuType,radioType,freq_mcu,SUPPLY_VOLTAGE_V); o_genericTimer[indexNode] = new SCTimerCounter (("timer"+s).c_str()); o_genericTimer_rf[indexNode] = new SCTimerCounter (("timer_rf"+s).c_str()); o_genericTimer[indexNode]->ClockTC(clk); o_genericTimer_rf[indexNode]->ClockTC(clk_hc05); o_genericMcu[indexNode]->clk(clk); o_genericMcu[indexNode]->allPacketsTransmitted(sig_allPacketsTransmitted[indexNode]); o_genericMcu[indexNode]->identSensor(identSensor_io[indexNode]); init_simul_i[indexNode].write(true); o_genericMcu[indexNode]->init_simul(init_simul_i[indexNode]); o_genericMcu[indexNode]->tc_reg_access.bind(o_genericTimer[indexNode]->reg_access_socket); o_genericMcu[indexNode]->tc_irq_socket.bind(o_genericTimer[indexNode]->irq); o_genericMcu[indexNode]->timeElapsed_mcu(timeElapsed_mcu[indexNode]); o_genericBattery[indexNode]->timeElapsed_mcu(timeElapsed_mcu[indexNode]); o_genericBattery[indexNode]->timeElapsed_radio(timeElapsed_radio[indexNode]); o_genericMcu[indexNode]->readSensorData(syncSensorsMcu[indexNode]); o_genericSensor[indexNode]->readSensorData(syncSensorsMcu[indexNode]); o_genericSensor[indexNode]->identSensor(identSensor_io[indexNode]); identSensor_io[indexNode]=0; for (int i=0; i< nbSensors; i++) { for (int j=0;j<fsampling;j++) { o_genericMcu[indexNode]->analogInput[i][j](sensorData[indexNode][j]); o_genericSensor[indexNode]->sensorAnalogOut[i][j](sensorData[indexNode][j]); } } o_genericMcu[indexNode]->paquetToTransmit(paquetToTransmit_io[indexNode]); o_genericMcu[indexNode]->batt_mcuState(batt_mcuState[indexNode]); o_genericBattery[indexNode]->batt_mcuState(batt_mcuState[indexNode]); o_genericBattery[indexNode]->batt_radioState(batt_radioState[indexNode]); o_genericMcu[indexNode]->radioINT(radioINT[indexNode]); o_genericMcu[indexNode]->sizeDataInRam(sizeDataInRam[indexNode]); o_genericMcu[indexNode]->radioCS(sig_radioCS[indexNode]); o_genericMcu[indexNode]->mcuInt(mcuInt[indexNode]); o_genericRadio[indexNode]->clk(clk_hc05); o_genericRadio[indexNode]->radioINT(radioINT[indexNode]); o_genericRadio[indexNode]->sizeDataInRam(sizeDataInRam[indexNode]); o_genericRadio[indexNode]->radioCS(sig_radioCS[indexNode]); o_genericRadio[indexNode]->mcuInt(mcuInt[indexNode]); o_genericRadio[indexNode]->sigFifoIn(sigMcuHC05[indexNode]); o_genericRadio[indexNode]->batt_radioState(batt_radioState[indexNode]); o_genericRadio[indexNode]->timeElapsed_radio(timeElapsed_radio[indexNode]); o_genericRadio[indexNode]->tc_reg_access.bind(o_genericTimer_rf[indexNode]->reg_access_socket); o_genericRadio[indexNode]->tc_irq_socket.bind(o_genericTimer_rf[indexNode]->irq); o_genericMcu[indexNode]->commandMode_CMD(commandMode_CMD[indexNode]); o_genericRadio[indexNode]->commandMode_CMD(commandMode_CMD[indexNode]); } ~emotica() { delete o_genericMcu[indexNode]; delete o_genericSensor[indexNode]; delete o_genericRadio[indexNode]; delete o_genericBattery[indexNode]; } }; SC_MODULE (signal_bind) { //sc_signal<int> indexNode; emotica *archEmotica_1 = NULL; SC_CTOR(signal_bind) { archEmotica_1 = new emotica("archEmotica_1"); //indexNode.write(1); //archEmotica_1->indexNode (indexNode); } ~signal_bind() { delete archEmotica_1; } }; int sc_main(int argc, char *argv[]) { signal_bind archEmotica("SIGNAL_BIND"); sc_start(); return 0; }
  16. I've noticed this in the PSS grammar: action_declaration ::= [ abstract ] action action_identifier [ action_super_spec ] { { action_body_item } }[ ; ] ... action_body_item ::= activity_declaration | overrides_declaration | constraint_declaration | action_field_declaration | symbol_declaration | covergroup_declaration | exec_block_stmt | static_const_field_declaration | action_scheduling_constraint | attr_group | compile_assert_stmt | inline_covergroup | action_body_compile_if ... constraint_declaration ::= [ dynamic ] constraint identifier { { constraint_body_item } } | constraint { { constraint_body_item } } | constraint single_stmt_constraint But example 3 goes like this: enum config_modes_e {UNKNOWN, MODE_A=10, MODE_B=20, MODE_C=35,MODE_D=40}; component uart_c { action configure { rand config_modes_e mode; constraint { mode != UNKNOWN; }; } }; The line constraint { mode != UNKNOWN; }; ^ | |Illegal semicolon? is a constraint_declaration used as an action_body_item inside an action_declaration. The grammar says that the constraint_declaration should not be terminated by a semicolon. Which is correct: the example or the grammar?
  17. Philipp A Hartmann

    Build error with 2.3.2

    The 'CMAKE_CXX_STANDARD' is specific to cmake. When you use automake/configure, you can configure the build by passing the '-std=c++11' flag directly to the configure call: ../configure ... 'CXXFLAGS=-std=c++11' Hope that helps, Philipp
  18. Nicole

    Build error with 2.3.2

    I am seeing this same issue trying to use SystemC 2.3.2 with a project compiling with C++11 standard. When installing SystemC, I used: ../configure prefix=/usr/local/systemc-2.3.2 CXXFLAGS=“-DCMAKE_CXX_STANDARD=11” I am compiling with clang 3.5, and for my project I have included the following in my compiler flags in the Makefile: -std=c++11 -I${SYSTEMC_HOME}/include -L${SYSTEMC_HOME}/lib-linux64 -lsystemc where SYSTEMC_HOME = /usr/local/systemc-2.3.2, which is my SystemC installation directory. The error I see is: In function `__cxx_global_var_init17': /usr/local/systemc-2.3.2/include/sysc/kernel/sc_ver.h:179: undefined reference to `sc_core::sc_api_version_2_3_2_cxx201103L<&sc_core::SC_DISABLE_VIRTUAL_BIND_UNDEFINED_>::sc_api_version_2_3_2_cxx201103L(sc_core::sc_writer_policy)' Any ideas? Thanks!
  19. Philipp A Hartmann

    Build error with 2.3.2

    SystemC 2.3.2 works fine with C++03, you just need to configure the C++ standard consistently between your application and the library build. In the (experimental) SystemC Cmake build setup, the selection always defaults to C++03, regardless of the default of the compiler. In your application build, you might not explicitly set the C++ standard on the command-line, giving you a different default version from your compiler. The behavior of the SystemC CMake setup could be improved here. Greetings from Duisburg, Philipp
  20. katang

    Build error with 2.3.2

    In my CMake I have the line set(CMAKE_CXX_STANDARD 11) and I did not configure SystemC before building it. I will try to do so. BTW: If that version works with standard 11 only, why is it not preconfigured?
  21. Thanks Justin for the update. I will follow-up from the Mantis.
  22. Roman Popov

    Error during installation

    Did you configured it with pthreads as described in release notes? In general, if possible you should use Visual Studio or MinGW on Windows. Cygwin is not widely used with SystemC so some bugs are possible. Also SystemC with cygwin/pthreads is much slower then with fibers.
  23. LevelDB

    Error during installation

    Hi, Sorry for my bad english, I'm trying to install systemC, I'm using the last version of Cygwin (64bit). This is the log of the testing suite I ran after I've compiled the source code. Do you know where I'm wrong? ================================================= SystemC 2.3.2: examples/sysc/test-suite.log ================================================= # TOTAL: 22 # PASS: 9 # SKIP: 0 # XFAIL: 0 # FAIL: 13 # XPASS: 0 # ERROR: 0 .. contents:: :depth: 2 FAIL: fft/fft_flpt/test.sh ========================== SystemC 2.3.2-Accellera --- Aug 3 2018 17:52:18 Copyright (c) 1996-2017 by all Contributors, ALL RIGHTS RESERVED ***ERROR: 0a1,34 > Reading in the samples... > Computing... > Writing the transform values... > Done... > Reading in the samples... > Computing... > Writing the transform values... > Done... > Reading in the samples... > Computing... > Writing the transform values... > Done... > Reading in the samples... > Computing... > Writing the transform values... > Done... > Reading in the samples... > Computing... > Writing the transform values... > Done... > Reading in the samples... > Computing... > Writing the transform values... > Done... > Reading in the samples... > Computing... > Writing the transform values... > Done... > Reading in the samples... > Computing... > Writing the transform values... > Done... > Reading in the samples... > End of Input Stream: Simulation Stops FAIL: fft/fft_fxpt/test.sh ========================== SystemC 2.3.2-Accellera --- Aug 3 2018 17:52:18 Copyright (c) 1996-2017 by all Contributors, ALL RIGHTS RESERVED ***ERROR: 0a1,18 > Reading in the samples... > Computing... > Writing the transform values... > Done... > Reading in the samples... > Computing... > Writing the transform values... > Done... > Reading in the samples... > Computing... > Writing the transform values... > Done... > Reading in the samples... > Computing... > Writing the transform values... > Done... > Reading in the samples... > End of Input Stream: Simulation Stops FAIL: simple_bus/test.sh ======================== SystemC 2.3.2-Accellera --- Aug 3 2018 17:52:18 Copyright (c) 1996-2017 by all Contributors, ALL RIGHTS RESERVED ***ERROR: 0a1,100 > 0 s top.master_d : mem[78:87] = (0, 0, 0, 0) > 100 ns top.master_d : mem[78:87] = (b, c, d, e) > 200 ns top.master_d : mem[78:87] = (b, c, d, e) > 300 ns top.master_d : mem[78:87] = (b, c, d, e) > 400 ns top.master_d : mem[78:87] = (1b, 1d, d, e) > 500 ns top.master_d : mem[78:87] = (26, 18, 1a, 2f) > 600 ns top.master_d : mem[78:87] = (26, 18, 1a, 2f) > 700 ns top.master_d : mem[78:87] = (26, 18, 1a, 2f) > 800 ns top.master_d : mem[78:87] = (31, 24, 27, 3d) > 900 ns top.master_d : mem[78:87] = (31, 24, 27, 3d) > 1 us top.master_d : mem[78:87] = (31, 24, 27, 3d) > 1100 ns top.master_d : mem[78:87] = (31, 24, 27, 3d) > 1200 ns top.master_d : mem[78:87] = (3c, 41, 46, 5e) > 1300 ns top.master_d : mem[78:87] = (3c, 41, 46, 5e) > 1400 ns top.master_d : mem[78:87] = (3c, 41, 46, 5e) > 1500 ns top.master_d : mem[78:87] = (47, 4d, 53, 6c) > 1600 ns top.master_d : mem[78:87] = (47, 4d, 53, 6c) > 1700 ns top.master_d : mem[78:87] = (47, 4d, 53, 6c) > 1800 ns top.master_d : mem[78:87] = (47, 4d, 53, 6c) > 1900 ns top.master_d : mem[78:87] = (62, 6a, 60, 7a) > 2 us top.master_d : mem[78:87] = (62, 6a, 72, 8d) > 2100 ns top.master_d : mem[78:87] = (62, 6a, 72, 8d) > 2200 ns top.master_d : mem[78:87] = (62, 6a, 72, 8d) > 2300 ns top.master_d : mem[78:87] = (6d, 76, 7f, 9b) > 2400 ns top.master_d : mem[78:87] = (6d, 76, 7f, 9b) > 2500 ns top.master_d : mem[78:87] = (6d, 76, 7f, 9b) > 2600 ns top.master_d : mem[78:87] = (78, 82, 8c, a9) > 2700 ns top.master_d : mem[78:87] = (88, 93, 9e, bc) > 2800 ns top.master_d : mem[78:87] = (88, 93, 9e, bc) > 2900 ns top.master_d : mem[78:87] = (88, 93, 9e, bc) > 3 us top.master_d : mem[78:87] = (93, 9f, ab, ca) > 3100 ns top.master_d : mem[78:87] = (93, 9f, ab, ca) > 3200 ns top.master_d : mem[78:87] = (93, 9f, ab, ca) > 3300 ns top.master_d : mem[78:87] = (9e, ab, b8, d8) > 3400 ns top.master_d : mem[78:87] = (ae, ab, b8, d8) > 3500 ns top.master_d : mem[78:87] = (ae, bc, ca, eb) > 3600 ns top.master_d : mem[78:87] = (ae, bc, ca, eb) > 3700 ns top.master_d : mem[78:87] = (b9, c8, d7, f9) > 3800 ns top.master_d : mem[78:87] = (b9, c8, d7, f9) > 3900 ns top.master_d : mem[78:87] = (b9, c8, d7, f9) > 4 us top.master_d : mem[78:87] = (c4, d4, d7, f9) > 4100 ns top.master_d : mem[78:87] = (c4, d4, e4, 107) > 4200 ns top.master_d : mem[78:87] = (d4, e5, f6, 107) > 4300 ns top.master_d : mem[78:87] = (d4, e5, f6, 11a) > 4400 ns top.master_d : mem[78:87] = (df, f1, 103, 128) > 4500 ns top.master_d : mem[78:87] = (df, f1, 103, 128) > 4600 ns top.master_d : mem[78:87] = (df, f1, 103, 128) > 4700 ns top.master_d : mem[78:87] = (df, f1, 103, 128) > 4800 ns top.master_d : mem[78:87] = (ea, fd, 110, 136) > 4900 ns top.master_d : mem[78:87] = (fa, fd, 110, 136) > 5 us top.master_d : mem[78:87] = (fa, 10e, 122, 149) > 5100 ns top.master_d : mem[78:87] = (105, 11a, 12f, 157) > 5200 ns top.master_d : mem[78:87] = (105, 11a, 12f, 157) > 5300 ns top.master_d : mem[78:87] = (105, 11a, 12f, 157) > 5400 ns top.master_d : mem[78:87] = (105, 11a, 12f, 157) > 5500 ns top.master_d : mem[78:87] = (110, 126, 13c, 165) > 5600 ns top.master_d : mem[78:87] = (110, 126, 13c, 165) > 5700 ns top.master_d : mem[78:87] = (120, 137, 14e, 165) > 5800 ns top.master_d : mem[78:87] = (12b, 143, 14e, 178) > 5900 ns top.master_d : mem[78:87] = (12b, 143, 15b, 186) > 6 us top.master_d : mem[78:87] = (12b, 143, 15b, 186) > 6100 ns top.master_d : mem[78:87] = (12b, 143, 15b, 186) > 6200 ns top.master_d : mem[78:87] = (136, 14f, 168, 194) > 6300 ns top.master_d : mem[78:87] = (136, 14f, 168, 194) > 6400 ns top.master_d : mem[78:87] = (136, 14f, 168, 194) > 6500 ns top.master_d : mem[78:87] = (146, 160, 17a, 1a7) > 6600 ns top.master_d : mem[78:87] = (151, 16c, 187, 1b5) > 6700 ns top.master_d : mem[78:87] = (151, 16c, 187, 1b5) > 6800 ns top.master_d : mem[78:87] = (151, 16c, 187, 1b5) > 6900 ns top.master_d : mem[78:87] = (15c, 178, 194, 1c3) > 7 us top.master_d : mem[78:87] = (15c, 178, 194, 1c3) > 7100 ns top.master_d : mem[78:87] = (15c, 178, 194, 1c3) > 7200 ns top.master_d : mem[78:87] = (16c, 189, 194, 1c3) > 7300 ns top.master_d : mem[78:87] = (177, 195, 1a1, 1e4) > 7400 ns top.master_d : mem[78:87] = (177, 195, 1a1, 1e4) > 7500 ns top.master_d : mem[78:87] = (177, 195, 1a1, 1e4) > 7600 ns top.master_d : mem[78:87] = (182, 1a1, 1ae, 1f2) > 7700 ns top.master_d : mem[78:87] = (182, 1a1, 1ae, 1f2) > 7800 ns top.master_d : mem[78:87] = (182, 1a1, 1ae, 1f2) > 7900 ns top.master_d : mem[78:87] = (182, 1a1, 1ae, 1f2) > 8 us top.master_d : mem[78:87] = (18d, 1ad, 1cd, 213) > 8100 ns top.master_d : mem[78:87] = (18d, 1ad, 1cd, 213) > 8200 ns top.master_d : mem[78:87] = (18d, 1ad, 1cd, 213) > 8300 ns top.master_d : mem[78:87] = (18d, 1ad, 1cd, 213) > 8400 ns top.master_d : mem[78:87] = (198, 1b9, 1da, 221) > 8500 ns top.master_d : mem[78:87] = (198, 1b9, 1da, 221) > 8600 ns top.master_d : mem[78:87] = (198, 1b9, 1da, 221) > 8700 ns top.master_d : mem[78:87] = (1b3, 1c5, 1e7, 22f) > 8800 ns top.master_d : mem[78:87] = (1b3, 1d6, 1f9, 242) > 8900 ns top.master_d : mem[78:87] = (1b3, 1d6, 1f9, 242) > 9 us top.master_d : mem[78:87] = (1b3, 1d6, 1f9, 242) > 9100 ns top.master_d : mem[78:87] = (1be, 1e2, 206, 250) > 9200 ns top.master_d : mem[78:87] = (1be, 1e2, 206, 250) > 9300 ns top.master_d : mem[78:87] = (1be, 1e2, 206, 250) > 9400 ns top.master_d : mem[78:87] = (1c9, 1ee, 213, 25e) > 9500 ns top.master_d : mem[78:87] = (1d9, 1ff, 225, 25e) > 9600 ns top.master_d : mem[78:87] = (1d9, 1ff, 225, 271) > 9700 ns top.master_d : mem[78:87] = (1d9, 1ff, 225, 271) > 9800 ns top.master_d : mem[78:87] = (1e4, 20b, 232, 27f) > 9900 ns top.master_d : mem[78:87] = (1e4, 20b, 232, 27f) FAIL: simple_fifo/test.sh ========================= SystemC 2.3.2-Accellera --- Aug 3 2018 17:52:18 Copyright (c) 1996-2017 by all Contributors, ALL RIGHTS RESERVED ***ERROR: 0a1 > V<9>isit www<1>.a<9>ccellera<1>.o<9>rg and s<1>ee<9> what Sy<1>st<9>emC can <1>do<9> for you<1> today!<1> FAIL: 2.1/forkjoin/test.sh ========================== SystemC 2.3.2-Accellera --- Aug 3 2018 17:52:18 Copyright (c) 1996-2017 by all Contributors, ALL RIGHTS RESERVED ***ERROR: 0a1,29 > Round robin thread 1 at time 100 ns > Round robin thread 2 at time 110 ns > Round robin thread 3 at time 120 ns > Round robin thread 4 at time 130 ns > Round robin thread 1 at time 140 ns > Round robin thread 2 at time 150 ns > Round robin thread 3 at time 160 ns > Round robin thread 4 at time 170 ns > Round robin thread 1 at time 180 ns > Round robin thread 2 at time 190 ns > Round robin thread 3 at time 200 ns > Round robin thread 4 at time 210 ns > Returned int is 0 > Thread 0 ending. > Thread 1 ending. > Thread 2 ending. > Thread 3 ending. > Thread 4 ending. > Thread 5 ending. > Thread 6 ending. > Thread 7 ending. > Thread 8 ending. > Thread 9 ending. > Test_function sees 3.14159 > Returned int is 3 > void_function sees 1.2345 > ref_function sees 9.8765 > Returned int is 9 > Done. FAIL: 2.1/reset_signal_is/test.sh ================================= SystemC 2.3.2-Accellera --- Aug 3 2018 17:52:18 Copyright (c) 1996-2017 by all Contributors, ALL RIGHTS RESERVED ***ERROR: 0a1,102 > 0 s: reset > 1 ns: 0 > 2 ns: 1 > 3 ns: 2 > 4 ns: 3 > 5 ns: 4 > 6 ns: 5 > 7 ns: 6 > 8 ns: 7 > 9 ns: 8 > 10 ns: 9 > 11 ns: 10 > 12 ns: 11 > 13 ns: reset > 14 ns: 0 > 15 ns: 1 > 16 ns: 2 > 17 ns: 3 > 18 ns: 4 > 19 ns: 5 > 20 ns: 6 > 21 ns: 7 > 22 ns: 8 > 23 ns: 9 > 24 ns: 10 > 25 ns: 11 > 26 ns: 12 > 27 ns: 13 > 28 ns: 14 > 29 ns: 15 > 30 ns: 16 > 31 ns: 17 > 32 ns: 18 > 33 ns: reset > 34 ns: 0 > 35 ns: 1 > 36 ns: 2 > 37 ns: 3 > 38 ns: 4 > 39 ns: 5 > 40 ns: 6 > 41 ns: 7 > 42 ns: 8 > 43 ns: 9 > 44 ns: 10 > 45 ns: 11 > 46 ns: 12 > 47 ns: 13 > 48 ns: 14 > 49 ns: 15 > 50 ns: 16 > 51 ns: 17 > 52 ns: 18 > 53 ns: reset > 54 ns: 0 > 55 ns: 1 > 56 ns: 2 > 57 ns: 3 > 58 ns: 4 > 59 ns: 5 > 60 ns: 6 > 61 ns: 7 > 62 ns: 8 > 63 ns: 9 > 64 ns: 10 > 65 ns: 11 > 66 ns: 12 > 67 ns: 13 > 68 ns: 14 > 69 ns: 15 > 70 ns: 16 > 71 ns: 17 > 72 ns: 18 > 73 ns: reset > 74 ns: 0 > 75 ns: 1 > 76 ns: 2 > 77 ns: 3 > 78 ns: 4 > 79 ns: 5 > 80 ns: 6 > 81 ns: 7 > 82 ns: 8 > 83 ns: 9 > 84 ns: 10 > 85 ns: 11 > 86 ns: 12 > 87 ns: 13 > 88 ns: 14 > 89 ns: 15 > 90 ns: 16 > 91 ns: 17 > 92 ns: 18 > 93 ns: reset > 94 ns: 0 > 95 ns: 1 > 96 ns: 2 > 97 ns: 3 > 98 ns: 4 > 99 ns: 5 > 100 ns: 6 > Done FAIL: 2.1/sc_export/test.sh =========================== SystemC 2.3.2-Accellera --- Aug 3 2018 17:52:18 Copyright (c) 1996-2017 by all Contributors, ALL RIGHTS RESERVED ***ERROR: 0a1,3 > 10 ns In Channel run() > 17 ns In Channel run() > 20 ns In Channel run() FAIL: 2.1/scx_barrier/test.sh ============================= SystemC 2.3.2-Accellera --- Aug 3 2018 17:52:18 Copyright (c) 1996-2017 by all Contributors, ALL RIGHTS RESERVED ***ERROR: 0a1,4 > 11000.000000 - c > 11000.000000 - b > 11000.000000 - a > Program completed FAIL: 2.1/scx_mutex_w_policy/test.sh ==================================== SystemC 2.3.2-Accellera --- Aug 3 2018 17:52:18 Copyright (c) 1996-2017 by all Contributors, ALL RIGHTS RESERVED ***ERROR: 0a1,3 > t1 got mutex at 1 ns > t2 got mutex at 11 ns > t3 got mutex at 21 ns FAIL: 2.1/specialized_signals/test.sh ===================================== SystemC 2.3.2-Accellera --- Aug 3 2018 17:52:18 Copyright (c) 1996-2017 by all Contributors, ALL RIGHTS RESERVED ***ERROR: 0a1,13 > ( m_in_bigint4, m_inout_bigint4, m_in_biguint4, m_inout_biguint4, m_in_int4, m_inout_int4, m_in_uint4, m_inout_uint4 ) = 012345678 > m_signal_bigint8 = 18 > m_signal_biguint8 = 027 > m_signal_int8 = 36 > m_signal_uint8 = 045 > m_signal_bigint8 = 12 > m_inout_bigint4 = 3 > m_signal_biguint8 = 045 > m_inout_biguint4 = 06 > m_signal_int8 = 78 > m_inout_int4 = 9 > m_signal_uint8 = 0ab > m_inout_uint4 = 0c FAIL: 2.3/sc_rvd/test.sh ======================== SystemC 2.3.2-Accellera --- Aug 3 2018 17:52:18 Copyright (c) 1996-2017 by all Contributors, ALL RIGHTS RESERVED ***ERROR: 1a2,133 > 0 1 ns > 0 2 ns > 1 2 ns > 0 3 ns > 1 4 ns > 2 4 ns > 2 5 ns > 3 5 ns > 1 6 ns > 2 7 ns > 3 8 ns > 4 8 ns > 4 9 ns > 5 9 ns > 5 10 ns > 6 10 ns > 3 11 ns > 4 12 ns > 5 13 ns > 6 14 ns > 7 20 ns > 7 21 ns > 8 21 ns > 8 22 ns > 9 22 ns > 9 23 ns > 10 23 ns > 6 24 ns > 7 25 ns > 8 26 ns > 9 27 ns > 10 28 ns > 11 28 ns > 11 29 ns > 12 29 ns > 12 30 ns > 13 42 ns > 13 43 ns > 14 43 ns > 14 44 ns > 15 44 ns > 10 45 ns > 11 46 ns > 12 47 ns > 13 48 ns > 14 49 ns > 15 50 ns > 16 50 ns > 16 51 ns > 17 51 ns > 17 52 ns > 18 52 ns > 18 53 ns > 19 71 ns > 19 72 ns > 20 72 ns > 20 73 ns > 21 73 ns > 15 74 ns > 16 75 ns > 17 76 ns > 18 77 ns > 19 78 ns > 20 79 ns > 21 80 ns > 22 80 ns > 22 81 ns > 23 81 ns > 23 82 ns > 24 82 ns > 24 83 ns > 25 107 ns > 25 108 ns > 26 108 ns > 26 109 ns > 27 109 ns > 27 110 ns > 28 110 ns > 21 111 ns > 22 112 ns > 23 113 ns > 24 114 ns > 25 115 ns > 26 116 ns > 27 117 ns > 28 118 ns > 29 118 ns > 29 119 ns > 30 119 ns > 30 120 ns > 31 150 ns > 31 151 ns > 32 151 ns > 32 152 ns > 33 152 ns > 33 153 ns > 34 153 ns > 34 154 ns > 35 154 ns > 35 155 ns > 36 155 ns > 28 156 ns > 29 157 ns > 30 158 ns > 31 159 ns > 32 160 ns > 33 161 ns > 34 162 ns > 35 163 ns > 36 164 ns > 37 200 ns > 37 201 ns > 38 201 ns > 38 202 ns > 39 202 ns > 39 203 ns > 40 203 ns > 40 204 ns > 41 204 ns > 41 205 ns > 42 205 ns > 42 206 ns > 43 248 ns > 43 249 ns > 44 249 ns > 44 250 ns > 45 250 ns > 36 251 ns > 37 252 ns > 38 253 ns > 39 254 ns > Program completed FAIL: 2.3/sc_ttd/test.sh ======================== SystemC 2.3.2-Accellera --- Aug 3 2018 17:52:18 Copyright (c) 1996-2017 by all Contributors, ALL RIGHTS RESERVED ***ERROR: 1a2,134 > 0 1 ns > 1 2 ns > 0 3 ns > 2 4 ns > 1 5 ns > 0 5 ns > 3 6 ns > 2 7 ns > 4 8 ns > 1 9 ns > 3 11 ns > 2 11 ns > 5 12 ns > 4 13 ns > 6 14 ns > 5 15 ns > 3 17 ns > 4 19 ns > 6 21 ns > 5 21 ns > 7 22 ns > 8 23 ns > 7 24 ns > 9 25 ns > 8 26 ns > 10 27 ns > 9 28 ns > 11 29 ns > 6 30 ns > 7 32 ns > 8 34 ns > 10 36 ns > 9 36 ns > 12 37 ns > 11 38 ns > 12 40 ns > 13 51 ns > 14 52 ns > 13 53 ns > 15 54 ns > 14 55 ns > 16 56 ns > 10 57 ns > 11 59 ns > 12 61 ns > 13 63 ns > 15 65 ns > 14 65 ns > 17 66 ns > 16 67 ns > 18 68 ns > 17 69 ns > 18 71 ns > 19 88 ns > 20 89 ns > 19 90 ns > 21 91 ns > 20 92 ns > 22 93 ns > 15 94 ns > 16 96 ns > 17 98 ns > 18 100 ns > 19 102 ns > 21 104 ns > 20 104 ns > 23 105 ns > 22 106 ns > 24 107 ns > 23 108 ns > 24 110 ns > 25 133 ns > 26 134 ns > 25 135 ns > 27 136 ns > 26 137 ns > 28 138 ns > 27 139 ns > 29 140 ns > 21 141 ns > 22 143 ns > 23 145 ns > 24 147 ns > 25 149 ns > 26 151 ns > 28 153 ns > 27 153 ns > 30 154 ns > 29 155 ns > 30 157 ns > 31 186 ns > 32 187 ns > 31 188 ns > 33 189 ns > 32 190 ns > 34 191 ns > 33 192 ns > 35 193 ns > 34 194 ns > 36 195 ns > 35 196 ns > 28 198 ns > 29 200 ns > 30 202 ns > 31 204 ns > 32 206 ns > 33 208 ns > 34 210 ns > 36 212 ns > 35 212 ns > 37 233 ns > 38 234 ns > 37 235 ns > 39 236 ns > 38 237 ns > 40 238 ns > 39 239 ns > 41 240 ns > 40 241 ns > 42 242 ns > 41 243 ns > 42 245 ns > 43 286 ns > 44 287 ns > 43 288 ns > 45 289 ns > 44 290 ns > 46 291 ns > 36 292 ns > 37 294 ns > 38 296 ns > 39 298 ns > Program completed FAIL: 2.3/simple_async/test.sh ============================== SystemC 2.3.2-Accellera --- Aug 3 2018 17:52:18 Copyright (c) 1996-2017 by all Contributors, ALL RIGHTS RESERVED ***ERROR: 1a2,5 > I'm busy! > Asked to stop at time 10 ns > The dog barks before the end of simulation > Program completed
  24. Thank you @Martin Barnasconi, That was exactly what it was happening. I had a <port>.read(<sample>) with a specific sample.
  25. @sharvil111- This would appear to be a valid bug in the RTL, and it is now being tracked in Mantis (https://accellera.mantishub.io/view.php?id=6745). We'll post an update here when the bug is resolved, hopefully in time for the 2017 1.0 release. -Justin
  26. Martin Barnasconi

    Error: System not scheduable

    It looks like you have a multi-rate system, i.e. somewhere you defined a <port>.set_rate(..) in a set_attributes callback. Now you try to access the n-th sample at this port, like <port>.read(<sample>), but the nth sample is higher than the rate specified. This means you have either the wrong rate, or reading a sample outside the range defined by the rate.
  27. Hi A colleague and I came up with the following solution which seems simple enough and works well. We simply overrode the start() task of our frontdoor class like so : class my_frontdoor extends uvm_reg_frontdoor....... task start(uvm_sequencer_base sequencer, uvm_sequence_base parent_sequence = null, int this_priority = -1, bit call_pre_post = 1); my_sema.get(); super.start(sequencer,parent_sequence, this_priority,call_pre_post); my_sema.put(); endtask; Ideally I would have liked to override the pre/post_start() hooks but suprisingly the pre_start is already called too late ( after the UVM_FATAL already fires). Salman
  28. Hi, I got the same problem with the scheduling whilst modeling a PID controller with PWM and DC motor. However, adding the 1 step delay in the output port of the feedback path, caused another error: SystemC-AMS: Access to sample >= rate not allowed for port: motor.in I don't understand why I need to change the input rate. Any tips?
  29. === Posted same query over here, but unfortunately got no response so far. Henceforth trying it out in latest forum === When jumping form run phase to extract phase, the UVM BCL somehow invokes the extract phase twice. But when jumping from run phase to final phase, the final phase is invoked once only. Here I am using uvm_domain to jump from one phase to another. In the following pseudo code, the jump does not happen for extract phase. Moreover the extract phase display is coming twice. While the jump happens gracefully when jumping to final phase. package pkg; import uvm_pkg::*; class env extends uvm_env; `uvm_component_utils(env) int m_delay; function new (string name, uvm_component parent); super.new(name, parent); endfunction function void build_phase(uvm_phase phase); if (!uvm_config_db#(int)::get(this, "", "delay", m_delay)) `uvm_fatal("", "Delay missing from config db") endfunction task run_phase(uvm_phase phase); `uvm_info(get_full_name(), "run_phase called", UVM_MEDIUM) phase.raise_objection(this); repeat(5) #(m_delay); phase.drop_objection(this); `uvm_info(get_full_name(), "run_phase returning", UVM_HIGH) endtask function void extract_phase(uvm_phase phase); `uvm_info(get_full_name(),"this is extract phase",UVM_LOW) endfunction function void check_phase(uvm_phase phase); `uvm_info(get_full_name(),"this is check phase",UVM_LOW) endfunction function void report_phase(uvm_phase phase); `uvm_info(get_full_name(),"this is report phase",UVM_LOW) endfunction function void final_phase(uvm_phase phase); `uvm_info(get_full_name(),"this is final phase",UVM_LOW) endfunction endclass class test extends uvm_test; `uvm_component_utils(test) function new (string name, uvm_component parent); super.new(name, parent); endfunction env m_env1; uvm_domain domain1; function void build_phase(uvm_phase phase); // Use different delays to see that domain1 and domain2 run independently uvm_config_db#(int)::set(this, "m_env1", "delay", 100); m_env1 = env::type_id::create("m_env1", this); domain1 = new("domain1"); m_env1.set_domain(domain1); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); #5; // this is for domain1 to jump to respective phase phase if(!$test$plusargs("JMP_FINAL_PH")) begin `uvm_info(get_type_name(),"Jumping to extract phase now...",UVM_LOW) domain1.jump(uvm_extract_phase::get()); // This calls extract phase twice!! //phase.jump(uvm_extract_phase::get()); // This calls extract phase once only end else begin `uvm_info(get_type_name(),"Jumping to final phase now...",UVM_LOW) domain1.jump(uvm_final_phase::get()); // This calls final phase once. Under any circumstance end phase.drop_objection(this); endtask endclass endpackage module top; import uvm_pkg::*; import pkg::*; initial run_test("test"); endmodule Output is as follows: // Jumping from run_phase to extract_phase: UVM_INFO @ 0: reporter [RNTST] Running test test... UVM_INFO phase_jump.sv(20) @ 0: uvm_test_top.m_env1 [uvm_test_top.m_env1] run_phase called UVM_INFO phase_jump.sv(66) @ 5: uvm_test_top [test] Jumping to extract phase now... UVM_INFO 1800.2-2017-0.9/src/base/uvm_phase.svh(1579) @ 5: reporter [PH_JUMP] phase post_shutdown (schedule uvm_sched, domain domain1) is jumping to phase extract UVM_INFO phase_jump.sv(28) @ 500: uvm_test_top.m_env1 [uvm_test_top.m_env1] this is extract phase UVM_INFO phase_jump.sv(28) @ 500: uvm_test_top.m_env1 [uvm_test_top.m_env1] this is extract phase UVM_INFO phase_jump.sv(31) @ 500: uvm_test_top.m_env1 [uvm_test_top.m_env1] this is check phase UVM_INFO phase_jump.sv(34) @ 500: uvm_test_top.m_env1 [uvm_test_top.m_env1] this is report phase UVM_INFO phase_jump.sv(37) @ 500: uvm_test_top.m_env1 [uvm_test_top.m_env1] this is final phase UVM_INFO 1800.2-2017-0.9/src/base/uvm_report_server.svh(802) @ 500: reporter [UVM/REPORT/SERVER] // Jumping from run_phase to final_phase: UVM_INFO @ 0: reporter [RNTST] Running test test... UVM_INFO phase_jump.sv(20) @ 0: uvm_test_top.m_env1 [uvm_test_top.m_env1] run_phase called UVM_INFO phase_jump.sv(71) @ 5: uvm_test_top [test] Jumping to final phase now... UVM_INFO 1800.2-2017-0.9/src/base/uvm_phase.svh(1579) @ 5: reporter [PH_JUMP] phase post_shutdown (schedule uvm_sched, domain domain1) is jumping to phase final UVM_INFO phase_jump.sv(37) @ 5: uvm_test_top.m_env1 [uvm_test_top.m_env1] this is final phase UVM_INFO 1800.2-2017-0.9/src/base/uvm_report_server.svh(802) @ 5: reporter [UVM/REPORT/SERVER] Can anyone let me know what am I missing anything over here?
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