Jump to content

All Activity

This stream auto-updates     

  1. Today
  2. Yesterday
  3. Last week
  4. Actually this is not going to work as it is quite unlikely that both events fire at the same delta cycle. So you would write something like void do_dff(){ if(enable.read()) q=d; } sc_ctor(){ SC_METHOD(do_dff); sensitive << clk; } The only option to concatenate events is to use sc_core::sc_event_and_list and sc_core::sc_event_or_list but those can only use in dynamic sensitivity (wait() for SC_THREADs and next_trigger() for SC_METHODs). Best
  5. Hi, Example , chosen a D-f/f void do_dff() { q=d; } sc_ctor() { sc_method(do_dff); sensitive<<enable && clk; } the method do_dff() should invoke only when both changes (enable and clk)
  6. Hi Guys I have a scenario where I have an target module in SystemC-TLM2 with a tlm_target_socket. I developed a UVM based verification env to verify that SystemC-TLM2 model. In UVM test bench I have an initiator module which calls b_transport with some payload and in SystemC-TLM2 target side I have the implementation of b_transport. I can see the the payload reaching on systemc side but when I change the payload (e.g. data or address) in b_transport implementation, the changes are not reflected on UVM initiator after the b_transport call returns. I am not able to understand what is going wrong. Any help or guidance will be highly appreciated, I am using Cadence UVM-ML for this. Thanks Khushi
  7. AmeyaVS

    SystemC code running with testbench

    Hello @ssingh.codesupport, There are multiple issues here. It would really good if you can go through the following discussions and develop an understanding about the SystemC simulation workflow. In-case you still have questions you can post you queries here. Hope it helps. Regards, Ameya Vikram Singh
  8. Eyck

    SystemC code running with testbench

    Well, there are several problems in your code: naming and sc_out input is counterintuitive - but this is minor you use a limited range integer and assign values outside this range. sc_in<2> is a 2.bit integer and can hold values from -2 to 1. it seems you did not understand and obey event scheduling, more see below So what you see in line 16-22 of the output is the initial invocation of tb::source(), tb::sink(), and statem::controller(). There tb::source() writes 11 to input_sig and statem::controller() write enable=false. Due to the write to input_sig tb::source(), tb::sink(), and statem::controller() get invoked again (the are sensitive to the value_changed event) as the output line 23-29 show. tb::sink() now writes the same value to input_sig again but this does not trigger any value_changed event. Since no process is sensitive to enable and no other events are left over the simulation kernel stops the simulation. As there is now wait statement in your model you do not see any time advancing, everything happens at time 0 (but in different delta cycles). To my experience you should use SC_THREAD when you have an active component (tb in your case), here you can easily implement an implicit statemachine and advance time. Since SC_METHODs are not allowed to block (call wait()) they are more suited to reacting components. If you describe the intention I can provide you an example on how to do this. Best regards -Eyck
  9. From http://www.asic-world.com/systemverilog/literal_values4.html string a; a = "This is multi line comment \n and this is second line"; /* Outputs: a = This is multi line comment^M and this is second line */ //You will have ^M which is the dos character for new line. if you write to a file with this line. If you want to avoid that, then the next solution should be used string tmg ={" \n" , "//periodic signal intf.KEYCONTROL_CLK \n" , "fork\n" , " begin\n" , " the_clock = 0;\n" , " forever begin\n" , " if(the_clock == 0)\n" , " #(5000000/2 * 1ps);\n" , " else\n" , " #((5000000-5000000/2) * 1ps);\n" , " the_clock=~the_clock;\n" , " end\n" , " end\n" , "join_none\n"}; $display ( tmg); Obviously, the second example is recommended
  10. ssingh.codesupport

    SystemC code running with testbench

    Hello, I am trying to run a basic systemc code which checks for the value of a given input and monitors the result. For future process of development (which might turn into a complex project), I want to execute the dut using my testbench file. I have attached the codes and the terminal output. The code is not able to pick up the correct integers or even the sc_timestamp() value. Since everything is attached, please have a look and suggest solutions. Regards SS systemc codes output
  11. ssingh.codesupport

    SystemC linking problem in Ubuntu

    Yes I have a separate main file, a separate testbench and another module for the DUT. There was an issue with the linker path but it's resolved now. I also ran the installation commands once more for proper working of the library -libsystemc.a. There is further issue with the result of the program which I better write in a new post as its a different topic. Thanks a lot!
  12. TLM2 is completely different from RTL type of connection. Interface won't work. Nor is there timing you can count on since it could be either AT or LT without timing. You also need to specify if you are interfacing between SV and SC or is this native SV UVM to UVM TLM2.
  13. Hi Guys I am very new to UVM and trying to play around with a small example(see below). In this example what I am observing that the following sequence(at each posedge) - first monitor run_phase is executed - rtl is executed - driver is executed due to this, I get the following output UVM_INFO example.sv(112) @ 10: uvm_test_top.m_env.m_agent.m_monitor [monitor] out = 0x0 in=x UVM_INFO example.sv(42) @ 10: uvm_test_top.m_env.m_agent.m_data_sequencer@@m_data_sequence.m_data_item [data_item] in = 0xd, out = 0x0 UVM_INFO example.sv(112) @ 30: uvm_test_top.m_env.m_agent.m_monitor [monitor] out = 0x0 in=d UVM_INFO example.sv(42) @ 30: uvm_test_top.m_env.m_agent.m_data_sequencer@@m_data_sequence.m_data_item [data_item] in = 0xa, out = 0x2 UVM_INFO example.sv(112) @ 50: uvm_test_top.m_env.m_agent.m_monitor [monitor] out = 0x1a in=a UVM_INFO example.sv(42) @ 50: uvm_test_top.m_env.m_agent.m_data_sequencer@@m_data_sequence.m_data_item [data_item] in = 0x4, out = 0x6 UVM_INFO example.sv(112) @ 70: uvm_test_top.m_env.m_agent.m_monitor [monitor] out = 0x14 in=4 UVM_INFO example.sv(42) @ 70: uvm_test_top.m_env.m_agent.m_data_sequencer@@m_data_sequence.m_data_item [data_item] in = 0xc, out = 0xc But I want the following order(at each posedge) - driver run_phase - rtl - monitor run phase so that monitor display correct output. How I can achieve this. Or is there some other way to get the correct output. Here is the complete code import uvm_pkg::*; `include "uvm_macros.svh" module dut( input clk, input [3:0] in, output reg [4:0] out ); always @ (posedge clk) begin $display("in=%h",in); out <= 2*in; end endmodule interface dut_if (input clk); logic [3:0] in; logic [4:0] out; endinterface module dut_wrapper(dut_if _if); dut dut0(.clk (_if.clk), .in (_if.in), .out (_if.out)); endmodule class data_item extends uvm_sequence_item; `uvm_object_utils(data_item) rand bit [3:0] in; rand bit [4:0] out; constraint c_in {in >=0;in<=15;} function new (string name = ""); super.new(name); endfunction virtual function void display (); `uvm_info (get_type_name (), $sformatf ("in = 0x%0h, out = 0x%0h", in,out), UVM_LOW); endfunction endclass class data_sequence extends uvm_sequence; `uvm_object_utils(data_sequence) data_item m_data_item; function new (string name="data_sequence"); super.new(name); endfunction virtual task body(); m_data_item = data_item::type_id::create("m_data_item"); repeat (4) begin start_item(m_data_item); assert(m_data_item.randomize()) finish_item(m_data_item); end endtask endclass class driver extends uvm_driver#(data_item); `uvm_component_utils(driver) data_item m_data_item; virtual dut_if m_dut_if; function new(string name,uvm_component parent); super.new(name,parent); endfunction function void build_phase(uvm_phase phase); super.build_phase(phase); assert(uvm_config_db #(virtual dut_if) :: get (this, "", "m_dut_if", m_dut_if)); endfunction task run_phase(uvm_phase phase); forever begin @(posedge m_dut_if.clk); seq_item_port.get_next_item (m_data_item); m_dut_if.in = m_data_item.in; m_data_item.display(); seq_item_port.item_done(); end endtask endclass class monitor extends uvm_monitor; `uvm_component_utils(monitor) virtual dut_if m_dut_if; uvm_analysis_port #(data_item) item_collected_port; data_item m_data_item; function new(string name, uvm_component parent); super.new(name, parent); item_collected_port = new ("item_collected_port", this); endfunction virtual function void build_phase (uvm_phase phase); super.build_phase (phase); assert(uvm_config_db #(virtual dut_if) :: get (this, "", "m_dut_if", m_dut_if)); endfunction task run_phase(uvm_phase phase); super.run_phase(phase); m_data_item = data_item::type_id::create ("m_data_item", this); forever @(posedge m_dut_if.clk) begin m_data_item.out = m_dut_if.out; `uvm_info (get_type_name (), $sformatf ("out = 0x%0h", m_data_item.out), UVM_LOW); //item_collected_port.write (m_data_item); end endtask endclass class agent extends uvm_agent; `uvm_component_utils(agent) driver m_driver; data_sequence m_data_sequence; uvm_sequencer#(data_item) m_data_sequencer; monitor m_monitor; function new(string name, uvm_component parent); super.new(name, parent); endfunction virtual function void build_phase(uvm_phase phase); super.build_phase(phase); m_driver = driver::type_id::create("m_driver",this); m_data_sequence = data_sequence::type_id::create("m_data_sequence",this); m_data_sequencer = uvm_sequencer#(data_item)::type_id::create("m_data_sequencer",this); m_monitor = monitor::type_id::create ("m_monitor", this); endfunction virtual function void connect_phase (uvm_phase phase); super.connect_phase (phase); m_driver.seq_item_port.connect (m_data_sequencer.seq_item_export); endfunction endclass class env extends uvm_env; `uvm_component_utils(env) agent m_agent; function new(string name, uvm_component parent); super.new(name, parent); endfunction virtual function void build_phase(uvm_phase phase); super.build_phase(phase); m_agent = agent::type_id::create("m_agent",this); endfunction endclass class my_test extends uvm_test; `uvm_component_utils(my_test) env m_env; virtual dut_if m_dut_if; function new(string name, uvm_component parent); super.new(name, parent); endfunction virtual function void build_phase(uvm_phase phase); super.build_phase(phase); m_env = env::type_id::create("m_env",this); assert(uvm_config_db #(virtual dut_if) :: get (this, "", "dut_if", m_dut_if)); uvm_config_db #(virtual dut_if) :: set (this, "*", "m_dut_if", m_dut_if); endfunction virtual function void end_of_elaboration_phase (uvm_phase phase); uvm_top.print_topology (); endfunction task run_phase(uvm_phase phase); phase.raise_objection(this); m_env.m_agent.m_data_sequence.start(m_env.m_agent.m_data_sequencer); phase.drop_objection(this); endtask endclass module top; bit clk; always #10 clk <= ~clk; dut_if m_dut_if(clk); dut_wrapper m_dut_wrapper(._if(m_dut_if)); initial begin uvm_config_db #(virtual dut_if)::set (null, "uvm_test_top", "dut_if", m_dut_if); run_test("my_test"); end endmodule
  14. In UVM verification env, do we need to use two monitor if I want to sample the input (to DUT)and output(from DUT) and compare them in scoreboard. In this case do I need to use two monitor, one on input and other on output ? Can a single monitor does the same job ? I tried but what I see by the time output arrives the input changes(for next set of inputs) Thanks
  15. Hi Guys I am trying to put in place a generic UVM verification env for TLM IPs. For RTL IPs we usually define the interface like(for simple adder) interface dut_if (input clk); logic [3:0] in1; logic [3:0] in2; logic [4:0] out; endinterface What the interface definition look like for TLM2 interfaces (for example if DUT has a target socket) Thanks Khushi
  16. David Black

    A void value confusion

    Based on what I see, the * shouldn't even be there at all since the -> takes care of it. Either use: mNeuron->dendrit[index].write(value); or (*mNeuron).dendrit[index].write(value); However, I'm more concerned that you're not using ports to access members of a module (assuming Dendrit_Set is not part of module Neuron). That violates a rather fundamental principle of SystemC. It's legal C++, but questionable SystemC.
  17. katang

    A void value confusion

    You are both right. However, I would formulate the error message something like 'You are attempting to use a void value' and would print the location pointer at after the '*' rather than at the beginning of 'value'
  18. AmeyaVS

    A void value confusion

    Hello @katang, The compiler message is quite right as mentioned by @Eyck. The Compiler sees the code something like this: void Dendrit_Set(int index, int value) { *(mNeuron->dendrit[index].write(value)); } Basically the operator precedence is at play here(refer here for more details). Compiler sees that you are trying to dereference a void type, since the write method of the sc_signal returns void. Hope it helps. Best Regards, Ameya Vikram Singh
  19. Eyck

    A void value confusion

    Well, actually the error message from the point of the compiler is quite right: using the '*'-operator you intent to dereference the return value of write() which is 'void'. BR
  20. kartikkg

    A void value confusion

    Can you share some more code ? Where are you calling the function Dendrit_Set
  21. katang

    A void value confusion

    I am sorry, the '*' is obsolete here. The error message, however, is strange, I think.
  22. katang

    A void value confusion

    In my testbench void Dendrit_Set(int index, int value) { *mNeuron->dendrit[index].write(value);} protected: Neuron* mNeuron; I receive the error message error: void value not ignored as it ought to be { *mNeuron->dendrit[index].write(value);} ^ The relevant declaration/definition typedef sc_dt::sc_uint<DENDRIT_WIDTH> SC_DENDRIT_TYPE; SC_MODULE(Neuron) { // Ports sc_signal<SC_DENDRIT_TYPE > dendrit[NO_OF_DENDRITS]; What is wrong here? (I simple do not understand the error message)
  23. Hello Guys I have a scenario where I have an initiator module on SystemC side and target module on UVL side. From initiator side, I call b_transport with some payload and in target side the data field is modified. What I am seeing that when b_transport returns on initiator module, the changes in data field is not reflected. On SystemC side, I have a thread with following function void run(){ int i = 4; while(i--){ cout<<" in run........"<<endl; tlm::tlm_generic_payload* trans = new tlm::tlm_generic_payload; sc_time delay = sc_time(100, SC_NS); trans->set_command(tlm::TLM_WRITE_COMMAND); uint64_t addr = 0x0; uint8_t data = 0xa5; uint32_t length = 1; trans->set_address(addr); trans->set_data_ptr( reinterpret_cast<unsigned char*>(&data)); trans->set_data_length(length); trans->set_streaming_width(length); trans->set_response_status(tlm::TLM_INCOMPLETE_RESPONSE); initiator_socket->b_transport(*trans,delay); cout<<"Result : 0xa5 vs 0x"<<hex<<+data<<endl; wait(delay); } } On UVM target side, my b_transport implementation is as follows task b_transport(uvm_tlm_generic_payload gp, uvm_tlm_time delay); byte unsigned data[]; gp.get_data(data); `uvm_info("INFO", $sformatf("entering b_transport with data[0] : 0x%x",gp.m_data[0]), UVM_LOW); data[0] = ~data[0]; gp.set_data(data); `uvm_info("INFO", $sformatf("exiting b_transport with data[0] : 0x%x",gp.m_data[0]), UVM_LOW); endtask and the output I am getting is UVM_INFO @ 0: reporter [RNTST] Running test SV:sv_top set by +UVM_TESTNAME... in run........ UVM_INFO sv_target.sv(31) @ 0: uvm_test_top.targ [INFO] entering b_transport with data[0] : 0xa5 UVM_INFO sv_target.sv(34) @ 0: uvm_test_top.targ [INFO] exiting b_transport with data[0] : 0x5a Result : 0xa5 vs 0xa5 in run........ UVM_INFO sv_target.sv(31) @ 100000: uvm_test_top.targ [INFO] entering b_transport with data[0] : 0xa5 UVM_INFO sv_target.sv(34) @ 100000: uvm_test_top.targ [INFO] exiting b_transport with data[0] : 0x5a Result : 0xa5 vs 0xa5 in run........ UVM_INFO sv_target.sv(31) @ 200000: uvm_test_top.targ [INFO] entering b_transport with data[0] : 0xa5 UVM_INFO sv_target.sv(34) @ 200000: uvm_test_top.targ [INFO] exiting b_transport with data[0] : 0x5a Result : 0xa5 vs 0xa5 in run........ UVM_INFO sv_target.sv(31) @ 300000: uvm_test_top.targ [INFO] entering b_transport with data[0] : 0xa5 UVM_INFO sv_target.sv(34) @ 300000: uvm_test_top.targ [INFO] exiting b_transport with data[0] : 0x5a Result : 0xa5 vs 0xa5 It seems that on UVM side the data field is updated well but on TLM side it is not reflected. Can you help me to understand what is going wrong here ? Thanks Khushi
  24. Eyck

    SystemC linking problem in Ubuntu

    I agree here with David, best would be to share the basic parts of your code as well as the complete commands and outputs From your description you have your DUT and your testbench in a separate file. You should compile them (inlcuding your main.cpp) into .o files e.g. by running something like g++ -I. -I$SYSTEMC_HOME/include -L. -L$SYSTEMC_HOME/lib-linux64 -c <cpp file here> and then link all .o file into your executable like: g++ -L$SYSTEMC_HOME/lib-linux64 -Wl,-rpath=§SYSTEMC_HOME/lib-linux64 -o main *.o -lsystemc -lm This is a basic C++ compile flow, see also here https://www.cprogramming.com/compilingandlinking.html or here: https://www3.ntu.edu.sg/home/ehchua/programming/cpp/gcc_make.html BR
  25. David Black

    SystemC linking problem in Ubuntu

    On the surface I would say you have a problem with your own code, but I cannot say much more because you did not share the code with us. At a minimum I would need to see main.cpp, but if you have other source files (e.g. state.cpp, which I would expect since any self-respecting C++ coder would put each class into its own CLASSNAME.cpp and CLASSNAME.h (or .hpp) file). Note: This has nothing to do with Ubuntu and likely little to do with the SystemC version.
  26. ssingh.codesupport

    SystemC linking problem in Ubuntu

    Hello, I am trying to execute a basic project in SystemC-2.3.2 with: 1. Module with DUT (.h and .cpp file) 2. Testbench (.h and .cpp file) 3. Top module (main.cpp) The version is : g++ --version g++ (Ubuntu 7.3.0-16ubuntu3) 7.3.0 Due to some linking error, I get the following error while compiling. g++ -I. -I$SYSTEMC_HOME/include -L. -L$SYSTEMC_HOME/lib-linux64 -Wl,-rpath=§SYSTEMC_HOME/lib-linux64 -o main main.cpp -lsystemc -lm /tmp/ccKTqv2Y.o: In function `statem::statem(sc_core::sc_module_name)': main.cpp:(....): undefined reference to `statem::controller()' This error is consistent for all the SC_METHOD declarations. Please let me know where I am going wrong. Any suggestions are welcome. Thank you!
  1. Load more activity
×