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  2. veeresh k

    clock generation in system c

    Hey ameya, Thanx for the reply. 🙂 I have gone through documentation,but am not getting it completely. By seeing the suggested api documentation from u,i am assuming that we will have a time period of 1ps along with 0.5 dutycycle by default and we are changing a bit of start value of clock by using sc_start(1,SC_NS) .We just got to declare it and mention it in trace file n we will get the waveform,ryt? As u can see in below waveform,i know the reason for reset and enable changes,but the clock waveform reason i dint get. N how can i change the clock waveform.Is it done by this sc_clock testclk("testclk",2,SC_NS,0.5,1,SC_NS). Note:-In test clock i am just randomly taking the no. .
  3. Hello @vasu_c, Can you let us know what platform you are using for the AArch64 build? and also, if possible the ABI specifications of the GCC compiler as well? Thanks and Regards, Ameya Vikram Singh
  4. AmeyaVS

    clock generation in system c

    Hello @veeresh k, This example does not have a dedicated clock generator. // These statements are what driving the clock signal to with High time of 1 ns and low time of 1 ns. for (i=0;i<10;i++) { clock = 0; sc_start(1, SC_NS);// Run simulation for 1 ns. clock = 1; sc_start(1, SC_NS);// Run simulation for 1 ns. } What message you receive from the SystemC kernel refers to the timescale of 1 ps e.g.: Info: (I702) default timescale unit used for tracing: 1 ps You can get the SystemC API documentation for the sc_clock from here: SystemC sc_clock api reference. If you need a sample you can find a use-case reference here(though a little bit-dated): https://github.com/AmeyaVS/SystemC_ramblings/blob/ff1a111063842bfcd6f5de6bb3db74917dc6331c/src/03_fir/firsytemmain.cpp#L26 Hope it helps. Regards, Ameya Vikram Singh
  5. Today
  6. veeresh k

    clock generation in system c

    Hi, I have came across this counter example from other website. Can u please tell me ,where have we intitialised the main clock. I know the default time period is 1ps,but i am not getting the start of the clock is from which point. I am not knowing the reason for its generation in waveform viewer. Thank you. Below is the code: #include "systemc.h" #include "design.cpp" int sc_main (int argc, char* argv[]) { sc_signal<bool> clock; sc_signal<bool> reset; sc_signal<bool> enable; sc_signal<sc_uint<4> > counter_out; int i = 0; // Connect the DUT first_counter counter("COUNTER"); counter.clock(clock); counter.reset(reset); counter.enable(enable); counter.counter_out(counter_out); sc_start(1, SC_NS); // Open VCD file sc_trace_file *wf = sc_create_vcd_trace_file("counter"); // Dump the desired signals sc_trace(wf, clock, "clock"); sc_trace(wf, reset, "reset"); sc_trace(wf, enable, "enable"); sc_trace(wf, counter_out, "count"); // Initialize all variables reset = 0; // initial value of reset enable = 0; // initial value of enable for (i=0;i<5;i++) { clock = 0; sc_start(1, SC_NS); clock = 1; sc_start(1, SC_NS); } reset = 1; // Assert the reset cout << "@" << sc_time_stamp() <<" Asserting reset\n" << endl; for (i=0;i<10;i++) { clock = 0; sc_start(1, SC_NS); clock = 1; sc_start(1, SC_NS); } reset = 0; // De-assert the reset cout << "@" << sc_time_stamp() <<" De-Asserting reset\n" << endl; for (i=0;i<5;i++) { clock = 0; sc_start(1, SC_NS); clock = 1; sc_start(1, SC_NS); } cout << "@" << sc_time_stamp() <<" Asserting Enable\n" << endl; enable = 1; // Assert enable for (i=0;i<20;i++) { clock = 0; sc_start(1, SC_NS); clock = 1; sc_start(1, SC_NS); } cout << "@" << sc_time_stamp() <<" De-Asserting Enable\n" << endl; enable = 0; // De-assert enable cout << "@" << sc_time_stamp() <<" Terminating simulation\n" << endl; sc_close_vcd_trace_file(wf); return 0;// Terminate simulation }
  7. Yesterday
  8. Last week
  9. This was recently discussed here. The assertion should fail because disable_assert is false at the start of the attempt.
  10. I recently encountered SVA code which results in different results on different simulators. I've shrunk it to a simple example here. I believe this code should cause an error, but it does not on all tools. Can someone comment on how the 2017 LRM should be interpreted (and perhaps on the code). (I sense someone will comment on the driving signals in the code.) module top; bit clk; logic sig1; logic disable_assert; always begin #5 clk=0; #5 clk=1; end initial begin disable_assert=1'b1; sig1 =1'b0; $display("Hello World"); $monitor($time," **** sig1:%0b disable_assert:%0b",sig1, disable_assert); repeat (3) @(posedge clk); @(posedge clk); sig1=0; disable_assert=1; @(posedge clk); sig1=1; disable_assert=1; //2a. assertion would fail, but it is disabled @(posedge clk); sig1=0; disable_assert=0; //2b. now assertion is enabled and should fail** @(posedge clk); sig1=0; disable_assert=1; #20; $finish(); end property as_disable_testing; @(posedge clk) disable iff (disable_assert) !sig1; endproperty assert property (as_disable_testing); endmodule : top Question: Should there be a timing error at comment 2b, or not? Code is here to play around with: https://www.edaplayground.com/x/njR Picture: https://docs.google.com/drawings/d/1qQB4dB5w8_1jx73xta46RbmLzkparaNcxHNdLgi8YNY/edit?usp=sharing These are my thoughts: // It seems this small code snippet should cause an error, but tool results differ. // // // NOTE: Yes, I realize that I am using tools from BEFORE 2017, but comparing results to the 2017 LRM. // What is the correct LRM interpretation? What comments do gurus have about this code? // // //1) Run the code with Aldec Riviera Pro 2015.06, Synopsys VCS 2014.10, and with Cadence Incisive 15.20. // RIVIERA PRO and IRUN show assertion failures. // VCS does not show assertion failure. // //2a) This is time when sig1=1 assertion 'would' fail, but it is disabled (disable_assert==1) //2b) **On next clock cycle the assertion set to be enabled (i.e. disable_assert==0). // The SystemVerilog 2017 LRM (1800.1-2017.pdf) describes the behaviour. // At the start of the 2b time slot (see page 64 of SystemVerilog LRM 1800.1-2017), // PREPONED REGION: the values of the assertion are sampled (sig1==1) // ACTIVE/INACTIVE/NBA regions: the values are updated (sig1,disable_assert) // (so you can use either blocking "=" // or you can use non-blocking "<=" // and you will get the same result) // So for this time slot: sig1==0, disable_assert=0 // OBSERVED REGION: this is where the assertion is evaluated, using values sampled from // the preponed region (so sig1==1). // However, the value of disable_assert is not from the // preponed region, but simply whatever the value is, // as assigned in the active/inactive/nba region. // // // Section 16.6 of the SystemVerilog LRM (1800.1-2017 states: "The expressions in a disable condition are evaluated using the current values of variables (not sampled) ..." I believe this means from whatever is set in the Active/NBA region of current time slot. // // Section 16.12 of the same document states: "If the disable condition is true at anytime between the start of the attempt in the Observed region, inclusive, and the end of the evaluation attempt, inclusive, then the overall //evaluation of the property results in disabled." // // My conclusion: The sig1 value from 2a will be used in 2b when disable_assert=0; ***Assertion should fail.*** // // Picture: https://docs.google.com/drawings/d/1qQB4dB5w8_1jx73xta46RbmLzkparaNcxHNdLgi8YNY/edit?usp=sharing
  11. veeresh k

    system c beginner

    Seriously david, Thanks a ton. 🙂 Thank you for letting me know the aspects which i need to cover. Presently i am working with counter and flip flop examples,which are good enough to be carried with intermediate c++ knowledge i think. But the moment, when i will be starting with prim and hierarchial channels, i believe i will be needing the advanced topics. Please ,correct me if i am wrong.
  12. sheridp@umich.edu

    AT Examples

    Is it just that it is inappropriate to try to model at this high level of abstraction--like locking a bus without an explicit arbiter--using AT?
  13. David Black

    system c beginner

    Here is a short list of topics in no particular order you need to be comfortable with in order to be have an easier time learning SystemC: [Note: Others might chime in with variations on this list (add/subtract), and this is not necessarily a complete list, but I am fairly certain if you are able to comfortably use the topics I list below, you will have very little trouble syntactically with learning SystemC. In addition to C++, it helps if you have some familiarity with event driven simulation (e.g. SystemVerilog or VHDL). Also, if you have deep knowledge in another OO language (e.g. Java or SystemVerilog), you might have an easier time learning the C++ part.] Difference between declaration and definition Pass by value vs pass by reference Use of const (5 distinct cases) Casting C++ style (4 types) Implicit vs explicit conversions Use of function overloading and how to deal with ambiguity issues Use of std::string Use of streaming I/O How to declare, define and use classes Definition of default constructor Purpose and syntax of copy constructor How to declare and use namespaces Operator overloading as member functions and global functions. The difference between overloading and overriding. Relationship between class and struct How to extend classes and multiple inheritance Purpose of public and private Storage types and lifetimes: static, automatic, dynamic How to properly use new and delete Use of pointers and understanding of issues with pointer arithmetic Use of arrays and issues Advantages and use of std::vector<> Use of try-catch and throw Use of initializer list in constructor and a proper understanding of the order of construction Polymorphism and RTTI RAII Rule of 4 (6 if using C++11 or later) How and where to define templates/generic programming (does not need to be deep knowledge - just the basics) Use of templates and nested templates. Definition of full and partial template specialization. Different types of constructors and destructors Use of virtual inheritance (hint: it's not polymorphism) Extra topics: More STL including at least std::map<>, std::set<> Boost Modern C++ users (2011 onward) should know about: nullptr Uniform initialization Use of auto Use of ranged for Lambda definition, binding and use constexpr std::unique_ptr<>m std::shared_ptr<>
  14. Ganesan R

    System C quite different from c++

    Thank you Sir. I finally got array of fifo objects after lot of efforts using SC_vector I apologize for the title of the post, but I meant only what worked for c++ was not working for system c in that particular line. Again sorry. The problem with beginners like me is that if something is not working we don't know what would have gone wrong. A lot of book reading is of little assistance in tracing out the error in debugging the error. This is where expert help is of timely assistance like Eyck comment yesterday. Again lot of thanks for all of you as I am getting past my major hurdle. Will keep posting any further problems I face in my design. R. Ganesan
  15. veeresh k

    system c beginner

    As of now,i am familiar with oops concepts and have an intermediate level c++ knowledge. Is it enough or do i need to get much more knowledge regarding c++. Because everytime,i am starting afresh and ending up with more and more doubts. Thank you.
  16. maehne

    system c beginner

    First, make sure that you are proficient in C++ as SystemC is a C++ library, which makes extensively use of advanced C++ features! Then, read a good introductory book on SystemC. I am personally not familiar with the SystemC Primer so cannot judge it. I found the book "SystemC from the Ground Up" by David C. Black, Jack Donovan et al. very helpful to learn SystemC.
  17. veeresh k

    system c beginner

    Hi, I am new to system c. I am trying to learn it step by step,but getting messed up with arrival of every new topic. Any suggestions for good book ? Currently i am studying system c primer by J.Bhasker. Please, help me out. Thank you.
  18. David Black

    System C quite different from c++

    First, the title of this post is completely nonsensical. SystemC is a library written in C++ and everything about it is C++. It is much more likely that you simply are not very proficient with C++. One aspect of SystemC I always warn newbies about is that SystemC uses pretty much all of the features of C++. You really cannot get by with just thinking C++ is merely a better C. You have to really know about polymorphism, function/operator overloading, templates, exception handling, STL libraries, and all things C++. If you do not, I suggest you get some deeper learning on C++. Your problem is that sc_module disallows copy construction. Prior to C++11, this was accomplished by declaring the copy constructor private, which is why you are getting the error. sc_vector really is a better way of creating an array of modules, and it looks as if somebody has given you this hint.
  19. I have sc_module class fifog. What I want is an array of fifog in the fashion fifog[0],fifog[1] etc. fifog fifogarray[2]={fifog("fifog231"),fifog("fifog232")} declare in sc_main will surely work in c++, but in system c it throws up an error 1> error C2248: 'sc_core::sc_module::sc_module' : cannot access private member declared in class 'sc_core::sc_module' even though I have all member functions and elements declared as public in fifog. If that line is commented the program quite compiles and runs. Why so? You can check this in attached file. Trying how to access data members of fifog[0], fifog[1] etc. in sc_main. Any help will be deeply appreciated. accelerra.txt
  20. I had gcc-4.8.5 available on the ARM machine we are using. I could reproduce the crash with gcc-4.8.5 as well. Thanks in advance for any suggestions.
  21. Ganesan R

    How to create an array of sc_module objects

    Thanks Eyck that helped Suppose sc_vector<fifog>fifog32("fifog32",4) is declared in SC_main fifog constructor is called four times But fifog32[0].FIFO_pointer is not working even in SC_main How to get fifog32[0].FIFO_pointer? Eager n thanking you
  22. David Black

    what is "argc" and "argv[]" in systemc?

    Doesn't make as much sense to those who use Windows and Visual Studio. Much more understandable if you use Linux. Tip: You can access those two arguments from anywhere in your SystemC design using the two functions: sc_argc() and sc_argv(), which are in the sc_core namespace. Keep in mind that they only provide access to c_str values. If you want to interpret a numeric value from the command-line, you will need to convert it yourself.
  23. Hi, it seems you lack a basic understanding of C/C++ visibility of variables. As fifog32 is declared a local variable in sc_main you can only access it in sc_main, it is unknow in any other function. BR
  24. Hi, These are the command line arguments argc and argv which are propagated from main(). See also https://stackoverflow.com/questions/3024197/what-does-int-argc-char-argv-mean#3024202 Best
  25. I don't know what is "argc" and "argv []" , Can you explain about this?And when does it change ? #include "systemc.h" int sc_main (int argc, char* argv[]) { cout<<"Value of argc="<<argc<<endl; cout <<"Value of argc[]="<<hex<<argc<<endl; return 0; }
  26. It seems that a forgotten comment in file src/uvmsc/factory/uvm_default_factory.cpp line 1044 seems to be the culprit. Only printing should be affected. However, we will check within the workgroup if other effects are to be expected. For now, changing if( !m_type_overrides.size() ) //&& !sorted_override_queues.size() ) to if( !m_type_overrides.size() && !sorted_override_queues.size() ) should solve your issue.
  27. Ganesan R

    How to create an array of sc_module objects

    Somehow I was able to get this work. But I have only one difficulty right now: How to access the member of individual class object in the attached file It is sc_vector of fifog elements of four. fifo_pointer should be accessible in c++ like this. What is the problem with me? fifog32[0].fifo_pointer Any help will be deeply appreciated as I am heavily struck up. R. Ganesan (Pl. ignore earlier post I was able to get new sc_vector(fifog,4) with constant size) fifog_15May_end_mod.txt
  28. Ganesan R

    How to create an array of sc_module objects

    Thanks Ameya Singh. I am attaching relevant code herewith. If I can get your contact details, I can get in touch with you as I need a lot of help. R. Ganesan fifog_13May2015_error.txt
  29. AmeyaVS

    How to create an array of sc_module objects

    Hello @Ganesan R, It seems you are trying to achieve the vector of vector instance, something like this: sc_vector < sc_vector < your module > > You can find necessary discussion on this here: http://forums.accellera.org/topic/5616-initialization-of-nested-sc_vector-sc_vector/ Without sample code it is very difficult to discern the scenario you are trying to replicate. Can you provide some minimal sample code? Regards, Ameya Vikram Singh
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