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  3. Dear All, I'm trying to record the transaction of UVM by using Irun(Candence). But I can't find any usage for that. But I find one tcl script as the below when I googling, #Probe waveforms database -open -shm -into waves.shm waves -default # -event probe -create -database waves top -all -depth all # -memories probe -create -database waves $uvm:{uvm_test_top} -all -depth all -dynamic #stop at the end of the build phase and enable full verbosity #messaging and transaction recording uvm_phase -stop_at -build_done run uvm_message UVM_FULL * #Enable transaction recording uvm_set "*" "recording_detail" UVM_FULL if {!$simvision_attached} { run; exit; }; But I really don't know how to use above tcl code in my uvm running code. This is my running code This is list.f -uvmhome $UVM_HOME -incdir ../sv +UVM_VERBOSITY=UVM_LOW ../sv/yapp_pkg.sv ./top.sv ~ and I run by using this way irun -f list.f ans here is what I've got the error message ncsim> database -open -shm -into waves.shm waves -default -event Created default SHM database waves ncsim> ncsim> #Probe all signals at all levels ( be careful for lager designs) ncsim> probe -create -database waves uart_ctrl_top -all -depth all ncsim: *E,PNOOBJ: Path element could not be found: uart_ctrl_top. ncsim> ncsim> #Probe assertion as transactions ncsim> probe -create -datebase waves uart_ctrl_top.uart_dut.reg.receiver -assertions -transaction -depth all ncsim: *E,UNKOPT: unrecognized option for the probe [-create] command (-datebase). ncsim> probe -create -datebase waves uart_ctrl_top.uart_dut.reg.transmitter -assertions -transaction ncsim: *E,UNKOPT: unrecognized option for the probe [-create] command (-datebase). ncsim> ncsim> #Probe my arrays ncsim> probe -create -datebase waves md_top -all -memories -depth all ncsim: *E,UNKOPT: unrecognized option for the probe [-create] command (-datebase). ncsim> ncsim> #Probe the entire UVM Testbench hierachy ncsim> probe -create -database waves uvm_pkg::uvm_top -all -depth all ncsim: *E,OBJACC: Object must have read access: uvm_pkg::uvm_top. ncsim> ncsim> #Run to end of build ncsim> uvm_phase -stop_at -end connect Created stop 1:907b0a6e:uvm ncsim> run Would you please help me How do I record all transaction of UVM by using irun? Thanks in advanded
  4. Hi, how can I, include uvm_library in the cadence INCISIVE tool? thanks,
  5. Roman Popov

    Seeking Feedback on Datatypes

    Some thoughts on these topics: During elaboration any C++ should be supported, including standard library. Language/library restrictions should only be imposed on process bodies (SC_THREADs and SC_METHODs). Otherwise SystemC synthesis would not be competitive vs languages focused on structure generation. Some design teams are already switching from SystemC to Chisel due to limitations in SystemC tools. std::array can be supported, but adds little value compared to C-style arrays. sc_vector should be supported. But unfortunately it only supports sc_object types. So I can't for example create sc_vector<sc_int<32>> to model RAM with elaboration-time defined size. std::vector allows expansion during simulation, that won't be synthesizable. I think it would be a good idea to extend sc_vector with non-sc_object types support. Also more flexible API can be added, like emplace_back(...) for elaboration-time programming. Attributes can't be used with template-based compile-time programming and elaboration-time programming. Macros will be the only way to program with attributes. That is bad. Instead, why not to to standardize a set of functions to pass synthesis directives? As usual, there is a compromise between simulation performance and flexibility of usage. I looked through proposals, and I think it would be nice to have both AC datatypes and improvement to existing bigint SystemC datatypes. From flexibility perspective, sc_unsigned and sc_signed are ideal, because they can be used both with template-based meta-programming and elaboration-time programming. So we have the same structural programming flexibility as in Chisel or MyHDL. AC datatypes are less flexible, but more efficient.
  6. Hi Mastrick, Thanks for the reply. Can we have similar replace argument for set_inst_override? that would make more sense and debug will be less complex. Also, it will enable more simple inst_override usage. Thanks, Chintan
  7. Hello @Philipp A Hartmann, It seems to be an issue with this test scenario.(systemc/1666-2011-compliance/living_dead_bug) I tried running the regression test suite on another system and except for this test, all the other tests passes. Regards, Ameya Vikram Singh
  8. Thank you for posting Chintan. I see the 1800.2-2017 standard says in "8.3.1.4.1 set_inst_override_by_type and set_inst_override_by_name": That says to me that when you gave your original commands to override master_base_seq twice with different override types, the first one should be applied, just as you saw. The set_type_override variations include a "replace" argument that controls whether the new or the older override has priority, so it can work either way.
  9. Hello @Philipp A Hartmann, I have probably seen this behavior in other regression tests also. But currently I do not recall all of them, this one was the first one to deadlock. I will try to run the regression test-suite with individual tests and post the results whenever I get a chance. Thanks and Regards, Ameya Vikram Singh
  10. Philipp A Hartmann

    Possible Bug/Regression in SystemC 2.3.2: Race Condition

    Hi Ameya, thanks for testing. As said before, unfortunately I cannot reproduce this on my end. I would need more details on the current behavior: The backtrace looks like there is something broken during model teardown. Have you seen other cases? Are all simulations with processes hanging in a similar way? (e.g. can you provide a full regression result?) Greetings from Duisburg, Philipp
  11. Hi, Recently I was working on updates to my environment and had to switch to set_inst_override from set_type_override to be able to override the base_sequence with a different sequence for different master agents. Code in base_test to start sequence on master sequencer :: master_base_seq seq = master_base_seq::type_id::create("seq",this,"masterName"); seq.start(top.virtual_sequencer.masterSequencer); Code in test for initial override :: master_base_seq::type_id::set_inst_override(master_user1_seq::get_type,"masterName.seq"); Now, later in test I need to change this override so that I can start another sequence on the same master. Coming from the set_type_override usage, i ended up writing below code :: master_base_seq::type_id::set_inst_override(master_user2_seq::get_type,"masterName.seq"); I observed that second time, the master still started the master_user1_seq instead the intended master_user2_seq. I printed the factory to see whether the override was registered or not, and I got below print :: # Instance Overrides: # # Requested Type Override Path Override Type # ------------------------- --------------------------------------------------- --------------------------------- # master_base_seq masterName.seq master_user1_seq # master_base_seq masterName.seq master_user2_seq After some experiments, I found that second time I need to use below override to be able to start the master_user2_seq on the master :: master_user1_seq::type_id::set_inst_override(master_user2_seq::get_type,"masterName.seq"); Above approach works, but have 2 issues :: 1. It's not consistent with the set_type_override usage. 2. This requires to keep track of last set_inst_override type in-order to override the inst with new type. I ended-up updating the uvm-1.2 library in-order to make the set_inst_override usage in-line with set_type_override as below:: In the check_inst_override_exists method in uvm_factory_.svh file - 1. I commented the same override_type check This way I only check whether the new request is for existing original_type and same full_inst_path. 2. When I get the match, I simply override the existing override with the new override_type and override_type_name. Updated code looks as below :: // check_inst_override_exists // -------------------------- function bit uvm_default_factory::check_inst_override_exists (uvm_object_wrapper original_type, uvm_object_wrapper override_type, string full_inst_path); uvm_factory_override override; uvm_factory_queue_class qc; if (m_inst_override_queues.exists(original_type)) qc = m_inst_override_queues[original_type]; else return 0; for (int index=0; index<qc.queue.size(); ++index) begin override = qc.queue[index]; if (override.full_inst_path == full_inst_path && override.orig_type == original_type && /*override.ovrd_type == override_type &&*/ //Commented check override.orig_type_name == original_type.get_type_name()) begin uvm_report_info("DUPOVRD",{"Instance override for '", original_type.get_type_name(),"' already exists: override type '", override_type.get_type_name(),"' with full_inst_path '", full_inst_path,"'"},UVM_HIGH); override.ovrd_type = override_type; // New Line override.ovrd_type_name = override_type.get_type_name(); //New Line return 1; end end return 0; endfunction With above change the set_inst_override usage becomes same as set_type_override. I am able to override inst for a object/component any number of time while using the same base_type and full_inst_path. Please, let me know, if this change or a batter solution can be incorporated in the next release. Thanks, Chintan
  12. hi, you are using uvm1.2 with the uvm11 version of the cadence extensions. please choose one of the following 1. use the cadence distributed version in your install 'irun -uvmhome CDNS-1.2 ....' (no need for any other uvm compile/flags ...) 2. you point to the right extensions 'irun -uvmhome ...yourpath... -uvmexthome <cdnsinstall>/tools/methodology/UVM/CDNS-1.2 ....' i also see that you are using a very old version of ius and it is suggested to use a more recent one. /uwe
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  14. Hello @Philipp A Hartmann, Thank you for your reply. Unfortunately even after applying the changes the issue still persists. In-case you need more inputs do let me know. Thanks and Regards, Ameya Vikram Singh
  15. Philipp A Hartmann

    Possible Bug/Regression in SystemC 2.3.2: Race Condition

    Hi Ameya, I currently don't have access to such new Linux platforms, but I may have a suspicion about a potential root cause. Can you please check, if it helps to change the sc_process_b::delete_process function in src/sysc/kernel/sc_process.cpp as follows: // if ( this != sc_get_current_process_b() ) if ( NULL == sc_get_current_process_b() ) Thanks and Greetings from Duisburg, Philipp
  16. Dear Ameya, It worked. Thank you! Ravi PS: I will update info at stackoverflow with the link for Eclipse 4.8 CDT. Hope you are OK with that.
  17. Hello @Roman Popov, It seems the issue is consistent with multiple different Linux OS with recent versions of GLIBC. From what I could figure out was the internal implementation for pthread mutex and condition variables have been updated. I will try to find the discussion on the same, but for now I think it would be better if someone from working group could also provide some insight into the issue. Regards, Ameya Vikram Singh
  18. Use a multi_pass_thru_socket and a simple loop (incomplete - extend as needed): #include <systemc> #include <tlm> #include <tlm_utils/simple_initiator_socket.h> #include <tlm_utils/multi_passthrough_initiator_socket.h> struct Broadcast : sc_core::sc_module tlm_utils::simple_target_socket target_socket<>; tlm_utils::multi_pass_through_initiator_socket initiator_socket<Broadcast>; SC_CTOR(Broadcast) : target_socket("target_socket") , initiator_socket("initiator_socket") { target_socket.register_b_transport( this, &Broadcast::b_transport ); } void b_transport(tlm::tlm_generic_payload& payload, sc_time& delay); }; void Broadcast::b_transport(tlm::tlm_generic_payload& payload, sc_time& delay) { for (size_t i=0; i<initiator_socket.size(); ++i) { initiator_socket[i]->b_transport(payload, delay); } } Of course you need to be careful with this because technically you probably need to copy the payload (i.e. create an individual transaction per target). If it is a an IGNORE_COMMAND and you use appropriately designed extensions, then it might work.
  19. Thanks Eych ! and is it possible to work with multi_passthrough_socket / tlm_base_socket to achieve this ?
  20. maehne

    SystemVerilog "program" scope

    It is up to the IEEE P1666 working group to decide, which currently experimental SystemC API features become official part of a future IEEE Std 1666 revision. The companies/people involved in the maintenance of the SystemC PoC simulator are also actively involved in this standardisation effort. The implementation of experimental features into the PoC implementation serve as a testbed to gain experience with them and collect feedback on their functionality, usability, and usefulness and real world applications. That is important input for the standardisation process.
  21. Actually you could use some kind of a router or broadcaster between the master and the target(s). Examples of this can be found here: or here: https://git.minres.com/SystemC/SystemC-Components/src/branch/master/incl/scc/router.h where the first one may be better suited as a stand-alone example HTH
  22. Hi all, have a single initiator and multiple target , i want to broadcast data to all the targets, how can i ??
  23. You may connect the sequencer to a dummy driver which gets the transaction which can transferred to RTL driver and TLM reference model thru TLM fifo. With this approach, you will have flexibility to keep transactions to RTL and reference model in SYNC or ASYNS(delay).
  24. AmeyaVS

    SystemC 2.3.2 on Ubuntu 18 and Eclipse

    Hello @RaviS, You can download the Latest Eclipse package from their website which does work on Ubuntu 18.04. Eclipse CDT download the package most pertinent to your system.(e.g. Ubuntu 64-bit download the Linux 64-Bit package.) The Eclipse IDE is very well supported on latest Linux Environments. Regards, Ameya Vikram Singh
  25. I have been using SystemC 2.3.1 with Ubuntu 17. With recent upgrade to Ubuntu 18 and SystemC 2.3.2, I am now unable to launch Eclipse. Error message led me to this link: https://stackoverflow.com/questions/3412617/java-lang-classnotfoundexception-org-eclipse-core-runtime-adaptor-eclipsestarte . Apparently Eclipse support for Ubuntu stopped at version 3.8, not the current 4.x. Support may be lacking going forward. Not sure whether it is worth staying with Eclipse. Please comment. Does anyone have experience with using Netbeans in Ubuntu for SystemC? Thanks!
  26. Hi folks, Is it possible to exclude individual fields in a register from checking of the hw reset value? How does one go about doing that, using the uvm_resource_db, (or another other way)? Thanks.
  27. Dear All, I'd like to dump the waveform using irun in UVM env. Currently I'm working on uvm-1.1d/examples/simple/basic_examples/module directory and INSICIVE152. the problem is that I don't know how to make wave dump file. Would you please help me let me know how to get the wave dump file with any example ?
  28. Dear All, I'm trying to compile the uvm-1.2 example. Basically, there examples in /uvm-1.2/example/simple/trivial/ Makefile.ius When I run " make -f Makefile.ius" then I've got the below error messages. m_handles[stream]=1; | ncvlog: *E,UNDIDN (INCISIVE151/tools/methodology/UVM/CDNS-1.1d/additions/sv//cdns_recording.svh,79|16): 'm_handles': undeclared identifier [12.5(IEEE)]. irun: *E,VLGERR: An error occurred during parsing. Review the log file for errors with the code *E and fix those identified problems to proceed. Exiting with code (status 1). irun: *E,UVMCXF: The process to compile the uvm extensions has failed. Add -uvmnocdnsextra to disable the addon package or point to the right version using -uvmexthome. What am I supposed to do to resolve this problem?
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