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  1. Yesterday
  2. Hi , Yes by adding the raise and drop phase objection the problem is solvable, but not all run phase can afford having these objections. For eg: top_uvm2 is a uvm component that has a run phase which has a thread that has to be run forever; like a driver component. It cannot have phaise raise or drop objections because of this reason. top_uvm2 is instantiated inside top_uvm1 component. top_uvm1 component has a phase raise and drop objections to make sure the phase is persistent and does not get over. If the threads in top_uvm2 are in a SC_JOIN or SC_JOIN_None implementation(both commented in code) the whole system works fine without any errors but the issue is with the SC_JOIN_ANY implementation. class top_uvm2: public uvm::uvm_component{ public: sc_event e1,e2; void fun1() { for(;;){ //Could be the main reason for different results between SC_JOIN and SC_JOIN_ANY cout<<"Current time is "<< sc_time_stamp() << endl; cout<< " =========== Main_fun1========" << endl; wait(e1); cout<<"Current time is "<< sc_time_stamp() << endl; } } void fun2() { cout<<"Current time is "<< sc_time_stamp() << endl; cout<< " =========== Main_fun2========" << endl; wait(e2); cout<<"Current time is "<< sc_time_stamp() << endl; } void run_phase(uvm::uvm_phase& phase) { uvm::uvm_component::run_phase(phase); cout<< " run: before fork/join main" << endl; /* SC_FORK sc_spawn(sc_bind(&top_uvm2::fun1, this)), sc_spawn(sc_bind(&top_uvm2::fun2, this)) SC_JOIN*/ /* void(sc_spawn(sc_bind(&top_uvm1::fun1, this))); void(sc_spawn(sc_bind(&top_uvm1::fun2, this)));*/ std::vector<sc_process_handle> process_handles; process_handles.push_back(sc_spawn(sc_bind(&top_uvm2::fun1, this)) ); process_handles.push_back(sc_spawn(sc_bind(&top_uvm2::fun2, this)) ); sc_event_or_list terminated_events; for(std::vector<sc_process_handle>::iterator it = process_handles.begin(); it != process_handles.end(); ++it) { terminated_events |= (*it).terminated_event(); } sc_core::wait( terminated_events ); //< wait for any process to exit for(std::vector<sc_process_handle>::iterator it = process_handles.begin(); it != process_handles.end(); ++it) { (*it).kill(); } cout << "run: after fork/join main" << endl; wait(50,SC_NS); cout<<"Current time is "<< sc_time_stamp() << endl; } top_uvm2 (uvm::uvm_component_name name="uvm_top2") : uvm::uvm_component( name ) { } }; class top_uvm1: public uvm::uvm_component{ public: top_uvm2* top_uvm_2; void fun1() { cout<<"Current time is "<< sc_time_stamp() << endl; cout<< " =========== fun1========" << endl; wait(10,SC_NS); top_uvm_2->e1.notify(); cout<<"Current time is "<< sc_time_stamp() << endl; } void fun2() { cout<<"Current time is "<< sc_time_stamp() << endl; cout<< " =========== fun2========" << endl; wait(40,SC_NS); cout<<"Current time is "<< sc_time_stamp() << endl; } void build_phase(uvm::uvm_phase& phase){ top_uvm_2 = new top_uvm2("top_2"); } void run_phase(uvm::uvm_phase& phase) { uvm::uvm_component::run_phase(phase); cout<< " run: before fork/join" << endl; phase.raise_objection(this); SC_FORK sc_spawn(sc_bind(&top_uvm1::fun1, this)), sc_spawn(sc_bind(&top_uvm1::fun2, this)) SC_JOIN cout << "run: after fork/join" << endl; wait(100,SC_NS); cout<<"Current time is "<< sc_time_stamp() << endl; phase.drop_objection(this); } top_uvm1 (uvm::uvm_component_name name="uvm_top1") : uvm::uvm_component( name ) { } }; int sc_main(int argc, char **argv) { top_uvm1* top_uvm_1; top_uvm_1 = new top_uvm1("top_1"); uvm::run_test(""); return 0; }
  3. Hi Kevin, you are missing the raising and dropping of an objection in the run_phase method (which would be required in SystemVerilog too) to prevent the early finish of the test sequence: void run_phase(uvm::uvm_phase& phase) { phase.raise_objection(this); [...] phase.drop_objection(this); } By adding this I get the desired result: UVM_INFO @ 0 s: reporter [RNTST] Running test ... run: before fork/join Current time is 0 s =========== fun1======== Current time is 0 s =========== fun2======== Current time is 20 ns run: after fork/join Current time is 60 ns UVM_INFO ../../../../uvm-systemc-1.0-beta2/src/uvmsc/report/uvm_default_report_server.cpp(666) @ 60 ns: reporter [UVM/REPORT/SERVER] --- UVM Report Summary --- ** Report counts by severity UVM_INFO : 1 UVM_WARNING : 0 UVM_ERROR : 0 UVM_FATAL : 0 ** Report counts by id [RNTST] 1 UVM_INFO @ 60 ns: reporter [FINISH] UVM-SystemC phasing completed; simulation finished
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  5. Thanks for the reply David. This is similar do what has been done in SVUnit. They provide their own UVM reporter and redefine `uvm_error to call that instead. I was hoping that UVM already had a more built-in mechanism for intercepting messages. If so, I could simply put the intercepted messages in a queue, verify that the queue contains the messages I expect and then pass/fail the test accordingly. I have to dig deeper and learn more but I was hoping that there would be a UVM action I can use or maybe uvm_report_catcher which by the name of it sounds related. Maybe these concepts can't be used for what I'm trying to do?
  6. Last week
  7. Philipp A Hartmann

    wait() is not allowed inside run_phase

    The error looks strange to me, as terminated_events is not destroyed before exiting run_phase, i.e. after the wait() has returned. However, I don't know how the objections are implemented in UVM SystemC and whether or how wait() is supported without raising an objection. Can you check with a debugger, if an exception is thrown while your run_phase function is inside the wait()? Hope that helps, Philipp
  8. David Black

    Verifying Verification Components

    I would do something I've previously done with SystemC (where uvm_error hails from). Basically, replaced the report handler with my own intercept to recategorize errors. Then added a mechanism to register "expected" errors, warnings, fatals. Prior to a point where an error was going to be injected, I would issue something like: begin_expect_error( "packet failure", 2 ); inject_error( ... ); wait_for_appropriate_time_or_event(); end_expect_error( "packet failure" ); If the report handler sees up to two errors, I would change the message severity to INFO and count off the expected error. At the end_expect_error call, I would check that exactly the number of expected errors occurred or consider it an error. Also, have to consider the possibility of the end_ call never happening.
  9. What is the preferred way to verify that a verification component calls uvm_error when it's supposed to without that error causing an error for my test? I know about SVUnit and its mocking capabilities but is it a way to do this within UVM?
  10. Hi Philip, Here is the output of the simulation. I have observed that it works fine when you include phase.raise() and phase.drop() objection inside the run_phase. Well there are instances where you cannot afford to have these objections in every run_phase. SystemC 2.3.2-Accellera --- Dec 18 2018 15:43:13 Copyright (c) 1996-2017 by all Contributors, ALL RIGHTS RESERVED Universal Verification Methodology for SystemC (UVM-SystemC) Version: 1.0-beta2 Date: 2018-10-24 Copyright (c) 2006 - 2018 by all Contributors See NOTICE file for all Contributors ALL RIGHTS RESERVED Licensed under the Apache License, Version 2.0 UVM_INFO @ 0 s: reporter [RNTST] Running test ... run: before fork/join top_1.thread_p_0 Current time is 0 s =========== fun1======== top_1.thread_p_1 Current time is 0 s =========== fun2======== Fatal: (F565) invalid use of sc_(and|or)_event_list: list prematurely destroyed In file: ../../../src/sysc/kernel/sc_event.cpp:679 In process: uvm_top.uvm_phase_run_process.thread_p_1.thread_p_0.exec_proc_run_top_1_0 @ 0 s Info: (I99) simulation aborted run_c++: line 9: 5962 Aborted (core dumped) ./sc_main.o
  11. Hi... the way that locking works is that when you next run virtuoso and it wants to try to lock the same file, it will look in the .cdslck file to see what machine the process is running, and the process id of the locking process. It will then ask to find out if that process is still running or not. If that process isn't running any more, then the lock will be reclaimed.
  12. sas73

    Log File Parsing

    Thanks @dave_59. I did a quick test with the commercial simulators available at EDA playground with the following error scenarios: 1. Assert with $error 2. Null object dereferencing Riviera-PRO would do a normal exit in both these scenarios, Cadence has a non-zero return code for both and Synopsis return non-zero for the null object dereferencing but not for the assert. I didn't check if there are option flags that would change this behavior but it seems that there are different opinions on how the return code should be used. Personally I would fail a test with a non-zero exit regardless of simulator strategy and log file contents. I would also prefer that the tools would use the return code for the errors they know about, at least as an option. Let's say I have a smaller project just using SystemVerilog with $error or VHDL asserts with error severity. The return code would give me pass/fail status if the assertions fail or if there is another problem like null object dereferencing . If it passed I don't care about the logs and if it failed they are small enough to be read manually. If I have a project using less specific error mechanisms like Verilog $display I would need parsing but the scope of parsing is reduced. If I have many long log files I may need scripting to mine them for the interesting events but in that case I rather have more machine readable formats that is well supported by scripting languages. XML or JSON for example. It would make the scripting easier and less error prone.
  13. Philipp A Hartmann

    wait() is not allowed inside run_phase

    Can you show the output of your simulation? And maybe add sc_get_current_process_handle().name() to the log statements to include the process name in the output. I would expect to at last see the output after the wait() in fun2. Secondly, you should check for (*it).terminated() and only kill() running processes in the termination loop.
  14. Hello Harshita, Please see the discussion in this topic: Best regards, Erwin
  15. Hi Bhargav, This is not allowed by SCR 6.25 on page 203 of the IEEE std. 1685-2014: "All ports referenced in an ad hoc connection shall reference the same number of bits. If no range is specified for a nonscalar port, then the full range from the port definition is presumed." Best regards, Erwin
  16. Hi! Since, component ipxact ports connection can be multidimensional i.e it can have multiple array and multiple vector. Then how we can define multiple port connection in ports??? like in this image only single vector connection is there. then how can i define for multidimensional???
  17. dave_59

    Log File Parsing

    The return code usually indicates successful completion of the tool and is unrelated to completion of the test. Non-zero return codes would be OS specific error codes. The SystemVerilog standard way of indicating pass/fail status is using the $info/$warning/$error/$fatal messages. Most tools are essentially catch the UVM reports and convert them to one of the SystemVerilog messages. They also have a way of detecting the most severe message issued during a run and you can use that information for determining pass/fail status.
  18. sas73

    Log File Parsing

    @David BlackWhat would you say is standard praxis for parsing logs to figure out pass/fail status? Find standard patterns for UVM errors + find simulator specific patterns for other errors + make sure there is a UVM report to catch silent errors stopping the simulation? Do people ever look at the return code? Testing at EDA Playground I see that some simulators return a non-zero code for some, but not all, errors. Why isn't this used more? Keeps me from knowing simulator specific error messages and makes the script more portable.
  19. Lynn Garibaldi

    Call for Participation - IEEE P1666

    The IEEE P1666 (SystemC) Working Group is now operating and looking for new members. If your company is a Corporate IEEE member and you use SystemC for your business, think about joining the P1666 Working Group to make the SystemC standard even better. If you have any questions about joining P1666, please contact Jerome Cornet (jerome.cornet@st.com), IEEE SystemC WG Chair, and Jonathan Goldberg (goldberg.j@ieee.org), IEEE representative for SystemC.
  20. I'm trying to find existing libraries of reusable assert macros that uses UVM messaging. For example checking equality and if it fails it would generate a message of expected and received values using uvm_error. What are my options?
  21. Thanks David. It sounds like no such tests are available. Open source projects in general are not always good at providing their test suites but I find it a bit odd that on open source library for verification doesn't provide the test suites showing how the library itself is verified. It would be easier for people to suggest improvements if they can verify whether or not such a modification breaks something else.
  22. sas73

    Log File Parsing

    Thanks David! I'll look into that.
  23. If your question on UVM is whether the repository is open to modifications, the answer is no. The UVM proof of concept library is carefully managed by Accellera as part of the standard's development. I cannot answer the question about test suites.
  24. David Black

    Log File Parsing

    Surprisingly, to me at least, a perl script I wrote in 1997 still appears to be popular. You can find it here: <https://github.com/dcblack/logscan/blob/master/README.md>.
  25. Hi, Are there any openly available (template) scripts to parse log files to find non-UVM error messages? Thanks
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