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  3. Hi, I have a doubt regarding an interface "X" being defined as : Driver code of the VIP: *********************************************** protected virtual X ChipIf; function void connect phase(uvm_phase phase); Y vif_container; super.connect_phase(phase); // Assigning virtual interface assert(uvm_config_object::get(this, "","V_IF_CHIP", temp)); $cast(vif_container, temp); ChipIf = vif_container.get_v_if(); endfunction : connect_phase ********************************************************** From the tb_top of the SoC , where the above VIP pkg is imported along with uvm pkg:*,please let me know how can I "set" the virtual ChipIf?
  4. Hi Ameya I have gone through the the link which you mentioned. if my understanding is correct,since simple sockets derive from standard sockets (tlm_initiator and target sockets) and these standard sockets are Inter operable ,so even simple sockets also supports interoperability. Regards Shashidhar
  5. Hello Shashidhar, You can look at the heading "Interoperability and the Base Protocol" on the same page on the Doulos TLM Tutorial page: https://www.doulos.com/knowhow/systemc/tlm2/tutorial__1/ Hopefully it helps, let me know. Regards, Ameya Vikram Singh
  6. Hi Akhila, functional coverage is not there yet. However, you can use any other implementation together with UVM-SC.
  7. thanks for the link ameya. Any idea about my 2nd doubt?? 2)And also simple_initiator_socket is part of tlm_utils and the feature which are part of tlm_utils does not support inter operable ,I would like to know why??
  8. Anyone who knows the current status of coverage support in UVM SC?
  9. Earlier
  10. Any help? please.
  11. It's in Regression library (separate download) at systemc-regressions-2.3.1a/tests/tlm/multi_sockets/MultiSocketSimpleSwitchAT.h:
  12. Ah..that make sense. Missed out on that one. Thanks!
  13. Hello, It is my first participation. I'm a master computer sciences student. I had program a code with SystemC 2.3.1 (includes TLM). I have some questions. Does SystemC 2.3.1 (includes TLM) includes TLM 1.0 ? What is the benefits of TLM 1.0? Can i use GTKWave with TLM 1.0 or it works just with SystemC RTL? What is the difference between TLM 1.0 and TLM 2.0 ? I would like to more understand TLM 1.0 any documents suggestions? Any help? Thanks.
  14. The philosophy behind nested classes is that they have access to private members of the parent class. If you want to do scoping, you're better off using packages (though it's not possible to define a nice hierarchical structure of packages).
  15. Are you trying to compile it on Windows? I don't think QuestaSim supports DPI under Windows (or at least not easily). At the same time, you don't really need to compile UVM itself when running QuestaSim, because the simulator comes packaged with the library and can reference that. * You can change the Makefile to not compile UVM anymore, only the testbench code for the example. * You can also disable DPI by adding the UVM_NO_DPI define (here you might also need to remove the lines from the Makefile that try to compile the C code). * Finally, what's missing there is the path to 'vpi_user.h'. You can add a '-I /path/to/vpi/user/h/inside/questa/installation/' to the GCC call, to tell it explicitly where it can find the file.
  16. The second argument for new(...) is the number of memory locations. You should call: new(..., 2048, 64, ...);
  17. It's not clear in this case what 'valid' means. I don't understand why in your case, when the model would generate '0100', the DUT will respond with '0101' after a '0101'.
  18. I am not able find mentioned example; i am checking in tlm2\TLM-2009-07-15\examples\tlm
  19. see the below image - ref OSCI TLM 2.0 LRM
  20. hi, I am sorry to misled you in my previous response. Target can return END_RESP - when the PHase need to be skipped. In this case, initiator may return TLM_COMPLETED. But is not mandatory. Thanks, Sudha.
  21. hi, Target /slave can send only END REQ and BEGIN_RESP. target can't send END_RESP. Thanks, Sudha.
  22. Hi, You can look into the previous discussion on the same. http://forums.accellera.org/topic/1603-simple-sockets-and-tlm-sockets/ You can also refer the Doulos TLM tutorial here about the tlm_utils. Regards, Ameya Vikram Singh
  23. Hi, Yes the TLM phase has to be in specific order. You can look into the examples folder for the "$SYSTEMC_HOME" installation folder, specifically at_1_phase, at_2_phase and at_4_phase sub-folder. $SYSTEMC_HOME/examples/tlm/ You can also look into a good documentation available in the "$SYSTEMC_HOME" install folder under doc folder, specifically slides: 36, 37, 38 about 1-Phase, 2-Phase, and 4-Phase transactions: $SYSTEMC_HOME/docs/tlm/release/TLM_2_0_presentation.pdf Hope this helps. Regards, Ameya Vikram Singh
  24. HI 1)I would like to know the difference between tlm_initiator_socket and simple_initiator_socket. From TLM LRM ,I understood that simple_initiator_socket. is also derived from tlm_initiator_socket and we need to register this socket with nb_transport_bw in the constructor. But after from this,is there any advantages of using it over tlm_initiator_socke. 2)And also simple_initiator_socket is part of tlm_utils and the feature which are part of tlm_utils does not support inter operable ,I would like to know why?? Regards Shashidhar
  25. Hi I have doubt about TLM Phase. Do i need use tlm phase in this specific order always (BEGIN_REQ,END_REQ,BEGIN_RESP and END_RESP)?? And if yes, what should be done when I send a BEGIN_REQ from the master side but get END_RESP from the slave side. (Should just stop the transaction??) Please help me out with this doubt
  26. Does UVM_SC has support for coverage bin and coverpoints? Want to know if user can add functional coverage classes. Thanks Akhila
  27. Hi All, I integrated SCV library in my environment and I am able to randomize my sequence item using SCV_EXTENSIONS and scv_smart_ptr. I still couldn't figure out the issue with UVM_DO* macros. But have found a way to randomize the transactions. Thanks Akhila
  28. Sorry its my mistake and i used set_time resolution at the time of elaboration, but didn't notice my sc_clock declaration. Before (error) sc_clock clk("clk",20, SC_FS); sc_set_time_resolution(1,SC_FS); After (start working) sc_set_time_resolution(1,SC_FS); sc_clock clk("clk",20, SC_FS); Thanks and closing the topic. Regards, Prasanna
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