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  3. define sc_main in VS 2017

    Don't change the default entry point and don't define main. Main is already pre-compiled inside the library!
  4. define sc_main in VS 2017

    Hello @AmeyaVS, Thanks for reply, does this mean that I only need to use sc_main function. I manually changed the entry point of the project in Visual Studio from main()to sc_main(), and I get this compiling error "a subsystem can't be inferred and must be defined".
  5. define sc_main in VS 2017

    Hello @Aaron0127, The entry point for creating the simulation models and starting simulation is supposed to be implemented within sc_main function. This was done to support the EDA tools vendors to support extensive debugging capability with their tools. In the available open source implementation the main function is provided by the SystemC library itself. Only the sc_main function implementation has to be provided by you. Hope it helps. Regards, Ameya Vikram Singh
  6. define sc_main in VS 2017

    Hi, I am new to SystemC, I have installed SystemC 2.3.2 successfully in Visual Studio 2017. The only problem that I have is with sc_main() function. The compiler complained the entry point cannot be found. I understand that the default entry point in VS is int main(). I have read IEEE Std 1666-2011 clause 4.3 about sc_main() and sc_elab_and_sim(). I tried to use following code to start simulation. But it failed. The compiler showed error message: "identifier "sc_eabl_and_sim" is undefined". int main(int arg, char* argv[]) { sc_elab_and_sim(arg, argv); //The rest code for simulation and testbench ... } How do I make sc_main(int arg, char* argv[]) function work in VS 2017? If not possible, how to properly call sc_eabl_and_sim(int arg, char* argv[]) in an int main(int arg, char* argv[]) to start a simulation?
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  9. Hello everyone, I'm performing the verification of a simple Sample and Hold implemented in SystemC-AMS. The Sample and Hold is modeled with the MOC ELN, the MOC TDF input signal source, and Sample and Hold output a port for the discrete domain. When the sample switch is closed for a long time the circuit has a low pass filter behavior, so the check consists of finding the cut-off frequency in this situation through the voltage gain (v_out / v_in = 0.707). However, this gain is only being achieved with frequencies much larger than the cutoff frequency. Codes are shown below Can anyone help? The V_in and Vout measurements are made by the read () method on the input signal "sc_core :: sc_signal <double> adc_in_source" and "sc_core :: sc_signal <double> adc_out". Thank you in advance. #include <systemc-ams.h> #include <cmath> class sample : public sc_module { public: sca_tdf::sca_in < bool > ctrl_lp; // CAPCOM input for the switch sc_in < double > in_src; // Analog signal input from the MUX sc_out < double > out; // Sampled signal output sca_eln::sca_tdf_rswitch key; // Switch ideal. Simulates sample switching. sca_eln::sca_node n1,n2,n3,n4; // electrical nodes sca_eln::sca_node_ref gnd; sca_eln::sca_c CI; // Low-pass filter input capacitance sca_eln::sca_r RI; // Internal filter resistance low pass filter sca_eln::sca_r RS; // External source resistance sca_eln::sca_de::sca_vsource vin_src; sca_eln::sca_de::sca_vsink vout; sample(sc_module_name name) : sc_module(name) , CI("CI") , RI("RI") , vin_src("vin_src") , vout("vout") , RS ("RS") , key("key") { vin_src.inp(in_src); vin_src.p(n1); vin_src.n(gnd); RS.value = 0e3; RS.n(n1); RS.p(n2); RI.value = 2e3; RI.n(n2); RI.p(n3); key.p(n4); key.n(n3); key.ctrl(ctrl_lp); key.ron; key.roff; CI.value = 40e-12; CI.q0 = 0.0; CI.p(n4); CI.n(gnd); vout.outp(out); vout.p(n4); // Vout.tdf_voltage(out); vout.n(gnd); } ~sample(){} }; #ifndef SRCS_H #define SRCS_H # include <systemc-ams.h> SCA_TDF_MODULE (srcs) { sca_tdf::sc_out<double> out_tdf_de; // output port srcs( sc_core::sc_module_name nm, double ampl_, double freq_, sca_core::sca_time Tm_) : out_tdf_de ("out_tdf_de") , ampl(ampl_) , freq_1(freq_) , Tm(Tm_) {} void set_attributes(); void processing(); public: double t; double ampl; // amplitude double freq_1; // frequency double data;// setup_param; int setup; sca_core::sca_time Tm; // module time step }; #endif // srcs_H #include "srcs.h" #include <cstdlib> /// for std::rand #include <cmath> void srcs::set_attributes() { set_timestep(Tm); } void srcs::processing(){ t = out_tdf_de.get_time().to_seconds(); // Get current time of the sample data = (ampl/2)*sin((2.0 * M_PI * freq_1 * t)) + ((ampl/2)); out_tdf_de.write(data); // Write value on output }
  10. User Guide for systemc 2.3.2

    I totally agree that it would be great if the example code from the "SystemC: from the ground up" book would be made available again on the internet. It is best to ask @David Black for that as he is one of the authors of the book. By the way, the second edition of the book has its own homepage: http://scftgu.com/ Unfortunately, it doesn't provide an archive with the example code sources either.
  11. User Guide for systemc 2.3.2

    Hi @maehne, I am reading the book "SystemC: from the ground up". It refers to some example codes at www.EklecticAlly.com but this link is not functional anymore. It would be a great help in my SystemC adventure if someone can give me those example codes. Thanks!
  12. Hi David I can not use sc_vector here because in real scenario, I have a interconnect implemented with following ports tlm::tlm_target_socket<32,tlm::tlm_base_protocol_types,0,SC_ZERO_OR_MORE_BOUND> In; tlm::tlm_initiator_socket<32,tlm::tlm_base_protocol_types,1,SC_ZERO_OR_MORE_BOUND> Out[N]; and in my platform, there are a case when two Out socket of an interconnect instance connected to same In socket of other interconnect. Thanks SumitJ
  13. I suggest that you read in IEEE Std 1666-2011 the introduction to the socket concept in clause 10.4 and then the rules for: multi-sockets in clause tlm_base_initiator_socket and tlm_base_target_socket in clause 13.2.4 of. ports in clause 5.12.4 exports in clause 5.13.4 Initiator sockets are derived from a port for interface method calls on the forward path and has an export for interface method calls on the backward path. For target sockets it is vice versa. Therefore, when you bind() sockets, the bind actually happens on the port and export. That's why the constraints on usage for ports and exports apply. For sc_port the following paragraph is relevant: For sc_export it is: Therefore, your example may not generate an error during compilation and elaboration, but may still disrespect the normal discipline of the module hierarchy.
  14. How to compare VCD files

    I guess you tried comparing traces in "impulse". In that case, you need to make sure that you have obtained the correct license. You need to unlock the "analyze" variant of impulse.
  15. Passing collected events to sensitive

    You can write function that will add collection of events to sensitivity. You can even overload operator << if that's what you want.
  16. How to compare VCD files

    Hi all, i tried comparing but i can not access the menu option. Any idea ? # Bruno
  17. Passing collected events to sensitive

    You are specifically referring to static sensitivity. Perhaps you should consider using dynamic sensitivity instead. You can use sc_event_and_list and sc_event_or_list to build up appropriate sensitivities.
  18. Backtrace with sc_report_error()

    Thanks for all of the suggestions. It turns out that the file name and line number in the output that I originally posted can be used to set a breakpoint and from there a call stack can be dumped (with bt). This approach is a bit like what Roman had suggested. I was also able to get sc_report_handler::set_action() to work. It's great to have all of the options suggested here.
  19. This happens because sc_port overloads operator[]. You need to use sc_vector tlm::tlm_initiator_socket<32,tlm::tlm_base_protocol_types,0,SC_ZERO_OR_MORE_BOUND> Out; SC_MODULE(Target) { sc_core::sc_vector< tlm::tlm_target_socket<32,tlm::tlm_base_protocol_types,1,SC_ZERO_OR_MORE_BOUND> > In; SC_CTOR(Target) : In("In", 2) { ... } //< Number of elemements selected via sc_vector constructor } initiator_inst->Out.bind(target_inst->In); Note: Above is pseudo-code (i.e. not in all the right places), and I have not taken time to verify the detail, but the principle of using sc_vector is correct. You may need to consult the literature.
  20. I have a scenario where I have a model (initiator) with following ports tlm::tlm_initiator_socket<32,tlm::tlm_base_protocol_types,0,SC_ZERO_OR_MORE_BOUND> Out; and another model(target) with following ports tlm::tlm_target_socket<32,tlm::tlm_base_protocol_types,1,SC_ZERO_OR_MORE_BOUND> In[2]; When I connect them as initiator_inst->Out.bind(target_inst->In[0]); initiator_inst->Out.bind(target_inst->In[1]); I get the following error Error: (E107) bind interface to port failed: interface already bound to port: port 'init_inst.tlm_base_initiator_socket_0' (tlm_initiator_socket) In file: ../../../../src/sysc/communication/sc_port.cpp:231 In above example, the Out socket has N=0 so it can connect to many number of sockets, then why I get this error Thanks SumitJ
  21. Hi, I'm using systemC to simulate a hierarchy of objects, where only the bottom of the hierarchy and the top are systemC modules. The objects in-between are organizational elements that allow me to create arbitrary collections of the bottom elements that I can then stamp out and efficiently wire to the top module. I want to both automate and hide the ports and channels necessary at each level. A stumbling block I've hit is how to handle the sensitivity of the top object. Currently I have as a method in the top object: SC_METHOD(send_op); for (int j=0;j<numRanks;j++) { for (int i=0;i<numPawns;i++) { sensitive << myRank[j]->receiveReady[i]; } } where Rank is the middle, non-SystemC organizing object, and the Pawns are the bottom-level SystemC objects that send a "Ready" event to the top object. I'd like to have SC_METHOD(send_op); for (int j=0;j<numRanks;j++) { sensitive << myRank[j]->get_sensitivities_from_rank(); } where get_sensitivies_from_rank is a function that returns the result of sensitive << (loop i over receiveReady[ i ]) for the container object Rank[j]. I can make a similar function that passes a collection of outputs for cout by using the ostream family, but this seems to be a much more sophisticated problem with sensitive. One of the errors I get appears to be that sensitive requires explicit channels in the << list, and anything indirect won't work. I've looked at sc_export, but that doesn't seem to work with static sensitivities...? I could also be doing this all the hard way; I've been using this as a way to learn systemC, so I'm open to any suggestions. Full code attached, if that helps. Thanks! rank.h rank.cc pawn.h pawn.cc Makefile king.h king.cc king_pawn_tst.cpp
  22. Thanks Roman, now this concept is clear for me.
  23. Hi Eyck I agree with you that it is allowed to direct connect an initiator(target) socket to target(initiator) socket but my question is related to hierarchical connections. As far as I know, it is allowed to hierarchically connect the following - initiator socket of child object to initiator socket of parent - target socket of child object to an target socket of parent but what about following - connecting initiator socket of child object to target socket of parent - connecting target socket of child object to initiator socket of parent In my understanding these should not be allowed but if I do that there is no compilation/elaboration errors Thanks Sumit
  24. C-API for SC-AMS

    Your arguments for foreign model reuse are valid and this is recognised by the people behind the modeling language definitions and simulators. That's why basically all common simulation tools provide some API to control the simulation programmatically from a foreign process including some means for data exchange (for stimuli and monitoring). Also, these tools usually provide a way to import foreign functions (usually at least those following the C calling conventions). By these ways, you can implement the synchronisation and data exchange mechanism between your models according to your needs. SystemC (AMS) only differs that the models are already written in C++, which provides even less friction to interact with the C APIs of other simulators. However, you have to keep in mind the simulation semantics of these models, which are imposed by the embedded simulation kernel during simulation. You have to make sure that you don't interfere with them through your API use in a way that disturbs the model execution. To that end, you should read up on the elaboration and simulation semantics of SystemC (AMS) in the respective LRMs. You will see there that both language standards define dedicated callbacks, which allow you to take action during all phases of elaboration and simulation, which facilitate the coupling of SystemC models with other simulators/modeling languages. You either have to implement the interface yourself or use the EDA tool vendor-specific solutions, which have been available for years, e.g., QuestaSim is capable to mixed SystemC/VHDL/SystemVerilog models. Another example is the SystemC AMS IDE COSIDE, which provides tool couplings to all major HDL simulators as well as to MATLAB/Simulink, dSPACE, and ngspice. For simple cases like you describe with your C application, which shall provide stimuli to your TDF model, you often get away with doing model synchronisation/data exchange via blocking read/write calls from within your SC_METHODs, SC_THREADs, or TDF processing() callbacks on some communication channel to your foreign model executed by another simulator. In the simplest case, this could be your stdin/stdout streams. Other popular options would be named pipes, sockets, or some some RPC API. The choice will largely depend on the modeling language/simulation tool, which you have on the other side. If they provide the possibility to import foreign C functions, they usually support all mentioned options. I think you might find interesting the technology demonstrator, which was presented by David C. Black at DVCon 2013 as part of the "Increasing Productivity with SystemC in Complex System Design and Verification" tutorial and made available on GitHub a while back: https://github.com/dcblack/technology_demonstrator You might also find other videos interesting, which are available from the Accellera website: http://videos.accellera.org/videos.html
  25. Use of callback before_end_of_elaboration

    In a current implementation sc_start() finishes elaboration and starts simulation. You can look into source code for details. But at very high level you can think of sc_start like this: void sc_start() { finish_elaboration(); // complete binding, call before_end_of_elaboration start_simulation(); // start scheduler } I recommend to run sc_start() in debugger step-by-step to understand what happens inside.
  26. Hi Sumit, of course it is allowed to bind an initator to a target socket, otherwise you would not be able connect an initiator to a target. But a can only once do this so usually you do it at the top level of connectivity. The picture below illustartes this, between module1 and module2 you have a binding of intor to target. +------------------------+ +----------------------+ | +---------------+ | | | | | | | | +-------------+ | | | | | | | | | | | intor | | | | target | | | | module +-+-+ +-+-+ intor to +-+-+ +-+-+ module | | | | | I +--+ I +-----------+ T +--+ T | | | | | +-+-+ +-+-+ target +-+-+ +-+-+ | | | | | | | | | | | | | | | | | | | +---------------+ | | +-------------+ | | module1 | |module2 | +------------------------+ +----------------------+ HTH -Eyck
  27. Hi Folks Is it allowed to connect an initiator port to a target port up in the hierarchy ? Is it allowed to connect an target port to a initiator port up in the hierarchy ? I assume no but what I observe that OSCI systemc implementation allows this. I tried to reproduce this problem with a small example(attached) where I have a component model with following ports tlm_utils::multi_passthrough_initiator_socket<model,32, tlm::tlm_base_protocol_types,0,SC_ZERO_OR_MORE_BOUND> master; tlm_utils::multi_passthrough_target_socket<model,32, tlm::tlm_base_protocol_types,0,SC_ZERO_OR_MORE_BOUND> slave; Then I create a subsystem with an instance of above component model and a following port tlm_utils::multi_passthrough_initiator_socket<model,32, tlm::tlm_base_protocol_types,0,SC_ZERO_OR_MORE_BOUND> master; Then if I connect model_inst->master.bind(master); // this is fine master.bind(model_inst->slave); // this should not allowed, I think I am attaching the complete code. Can you help me to understand whether it is allowed ? Thanks Sumit test.cpp
  28. Thanks Roman, a similar question: When exactly the elaboration and simulation process starts in SystemC? From my understanding, the elaboration starts when I instantiate the top module in sc_main and simulation starts when I call "sc_start" function. I failed to find the answer in SystemC IEEE_1666 stardard reference manual, could you please give me some hints?
  29. C-API for SC-AMS

    Hi, Thanks, for the explanation. If the intention is that of staying within SystemC/C/C++ then, this is a closed System which works well. It can do great things in a cost-effective way. However, I think this would be a minimalist way of looking at the application. In the everyday work, models do exist in different environments and I would like to reuse them rather than redo them. If someone has a model in Octave, I want to link to it (Octave, also describes ways to use it with other applications). If there is a model in spice (ngspice) I want to link to it and use it. If someone has a model in Verilog. I want to use it too. In the same way, models available in SC/SC-AMS should be easily re-used in other application/external tools without needed to REwrite the SC* model into another language (which might come with pain anyway). So this is really not trying to reinvent the wheel all the time and being productive. Also, REDOing them means spending extra money and time and if these are not an issue, there might be technical implications like missing expertise in teams and/or limitation of that particular environment. Other examples are: connecting the output of your model to different processing libraries (could use a file but is not the point here) in real time and based on that, change the stimuli/parameters. Shipping to costumes and/or interfacing with their environments Interacting with hardware (an FPGA or an analogue test-chip) If as you say we develop a system and prototype it within SC-AMS, It would be good to move vertically between prototype level and implementation level by means of REusing the already developed model. This is the best way to communicate intention and execute the model at different levels vertically. If the environments, system-level design and implementation level design, are different there need to be a way to enable what I mentioned. So, I believe that an expert programmer can get around and find more solutions, but I am an engineer and I design circuits and do models of them, and I feel my time needs to go more into this direction rather than trying to solve the software problem. In my simple example, I have an RC filter (ELN) with a TDF driver. Self-contained all is fine. But when I want to use a C-Program to change the input of the filter instead... I can get into so many troubles and I am already wrapping C++ into C- supported structured and referring to them as "extern" all in a "C-API". I will accept that I have limited knowledge to cover this topic, but I am also seeing that there are not many examples around (books, LRM, SC-AMS user guide, conferences). Other tools (some I mentioned) are seeing integration and interfacing being important and therefore they provide documentation, examples and eventually the full API. The same applies to SC/SC-AMS. Answering your question... This is what is missing. I think. I like this quote from Ezra Pound. “The sum of human wisdom is not contained in any one language, and no single language is capable of expressing all forms and degrees of human comprehension"
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